div16.vhd

在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY div16 IS
	PORT(clk             :IN  STD_LOGIC;
         div16             :out std_logic);
         END div16;

ARCHITECTURE arc OF div16 IS
SIGNAL counter: integer range 0 to 15;
BEGIN
PROCESS(clk)
BEGIN
	IF(clk'event AND clk='1')THEN
		case counter is
       when 0=>counter<=counter+1;
          div16<='1';
       when 1 to 14=>counter<=counter+1;
          div16<='0';
       when 15 =>counter<=0;
          div16<='0';
       when others=>counter<=0;
          div16<='0';
    end case;
   END IF;
END PROCESS;
END arc;