📄 ztja.rpt
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-- Node name is '~510~6'
-- Equation name is '~510~6', location is LC1_B11, type is buried.
-- synthesized logic cell
_LC1_B11 = LCELL( _EQ046);
_EQ046 = b0 & b6 & keyin0 & keyin6
# !b0 & b6 & !keyin0 & keyin6
# b0 & !b6 & keyin0 & !keyin6
# !b0 & !b6 & !keyin0 & !keyin6;
-- Node name is '~510~7'
-- Equation name is '~510~7', location is LC3_B11, type is buried.
-- synthesized logic cell
_LC3_B11 = LCELL( _EQ047);
_EQ047 = b4 & b5 & keyin4 & keyin5
# b4 & !b5 & keyin4 & !keyin5
# !b4 & b5 & !keyin4 & keyin5
# !b4 & !b5 & !keyin4 & !keyin5;
-- Node name is '~510~8'
-- Equation name is '~510~8', location is LC1_B13, type is buried.
-- synthesized logic cell
_LC1_B13 = LCELL( _EQ048);
_EQ048 = b2 & b3 & keyin2 & keyin3
# b2 & !b3 & keyin2 & !keyin3
# !b2 & b3 & !keyin2 & keyin3
# !b2 & !b3 & !keyin2 & !keyin3;
-- Node name is '~510~9'
-- Equation name is '~510~9', location is LC4_B13, type is buried.
-- synthesized logic cell
_LC4_B13 = LCELL( _EQ049);
_EQ049 = b10 & b11 & keyin10 & keyin11
# b10 & !b11 & keyin10 & !keyin11
# !b10 & b11 & !keyin10 & keyin11
# !b10 & !b11 & !keyin10 & !keyin11;
-- Node name is '~510~10'
-- Equation name is '~510~10', location is LC6_B14, type is buried.
-- synthesized logic cell
_LC6_B14 = LCELL( _EQ050);
_EQ050 = _LC1_B11 & _LC1_B13 & _LC3_B11 & _LC4_B13;
-- Node name is '~510~11'
-- Equation name is '~510~11', location is LC2_B7, type is buried.
-- synthesized logic cell
_LC2_B7 = LCELL( _EQ051);
_EQ051 = b22 & b23 & keyin22 & keyin23
# b22 & !b23 & keyin22 & !keyin23
# !b22 & b23 & !keyin22 & keyin23
# !b22 & !b23 & !keyin22 & !keyin23;
-- Node name is '~510~12'
-- Equation name is '~510~12', location is LC1_B7, type is buried.
-- synthesized logic cell
_LC1_B7 = LCELL( _EQ052);
_EQ052 = b30 & b31 & keyin30 & keyin31
# b30 & !b31 & keyin30 & !keyin31
# !b30 & b31 & !keyin30 & keyin31
# !b30 & !b31 & !keyin30 & !keyin31;
-- Node name is '~510~13'
-- Equation name is '~510~13', location is LC3_B15, type is buried.
-- synthesized logic cell
_LC3_B15 = LCELL( _EQ053);
_EQ053 = b28 & b29 & keyin28 & keyin29
# b28 & !b29 & keyin28 & !keyin29
# !b28 & b29 & !keyin28 & keyin29
# !b28 & !b29 & !keyin28 & !keyin29;
-- Node name is '~510~14'
-- Equation name is '~510~14', location is LC7_B1, type is buried.
-- synthesized logic cell
_LC7_B1 = LCELL( _EQ054);
_EQ054 = b1 & b27 & keyin1 & keyin27
# b1 & !b27 & keyin1 & !keyin27
# !b1 & b27 & !keyin1 & keyin27
# !b1 & !b27 & !keyin1 & !keyin27;
-- Node name is '~510~15'
-- Equation name is '~510~15', location is LC7_B14, type is buried.
-- synthesized logic cell
_LC7_B14 = LCELL( _EQ055);
_EQ055 = _LC1_B7 & _LC2_B7 & _LC3_B15 & _LC7_B1;
-- Node name is '~510~16'
-- Equation name is '~510~16', location is LC3_B13, type is buried.
-- synthesized logic cell
_LC3_B13 = LCELL( _EQ056);
_EQ056 = b20 & b21 & keyin20 & keyin21
# b20 & !b21 & keyin20 & !keyin21
# !b20 & b21 & !keyin20 & keyin21
# !b20 & !b21 & !keyin20 & !keyin21;
-- Node name is '~510~17'
-- Equation name is '~510~17', location is LC7_B7, type is buried.
-- synthesized logic cell
_LC7_B7 = LCELL( _EQ057);
_EQ057 = b18 & b19 & keyin18 & keyin19
# b18 & !b19 & keyin18 & !keyin19
# !b18 & b19 & !keyin18 & keyin19
# !b18 & !b19 & !keyin18 & !keyin19;
-- Node name is '~510~18'
-- Equation name is '~510~18', location is LC1_B1, type is buried.
-- synthesized logic cell
_LC1_B1 = LCELL( _EQ058);
_EQ058 = b17 & b26 & keyin17 & keyin26
# !b17 & b26 & !keyin17 & keyin26
# b17 & !b26 & keyin17 & !keyin26
# !b17 & !b26 & !keyin17 & !keyin26;
-- Node name is '~510~19'
-- Equation name is '~510~19', location is LC6_B15, type is buried.
-- synthesized logic cell
_LC6_B15 = LCELL( _EQ059);
_EQ059 = b24 & b25 & keyin24 & keyin25
# b24 & !b25 & keyin24 & !keyin25
# !b24 & b25 & !keyin24 & keyin25
# !b24 & !b25 & !keyin24 & !keyin25;
-- Node name is '~510~20'
-- Equation name is '~510~20', location is LC8_B14, type is buried.
-- synthesized logic cell
_LC8_B14 = LCELL( _EQ060);
_EQ060 = _LC1_B1 & _LC3_B13 & _LC6_B15 & _LC7_B7;
-- Node name is ':510'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ061);
_EQ061 = _LC5_B14 & _LC6_B14 & _LC7_B14 & _LC8_B14;
-- Node name is ':627'
-- Equation name is '_LC2_C15', type is buried
!_LC2_C15 = _LC2_C15~NOT;
_LC2_C15~NOT = LCELL( _EQ062);
_EQ062 = !keyvalue2
# !keyvalue3
# !keyvalue1
# !keyvalue0;
-- Node name is ':749'
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = LCELL( _EQ063);
_EQ063 = keyvalue0 & keyvalue1 & !keyvalue2 & keyvalue3;
-- Node name is '~1293~1'
-- Equation name is '~1293~1', location is LC1_C3, type is buried.
-- synthesized logic cell
_LC1_C3 = LCELL( _EQ064);
_EQ064 = m_state~2
# m_state~1
# !m_state~5
# m_state~3;
-- Node name is '~1310~1'
-- Equation name is '~1310~1', location is LC3_C3, type is buried.
-- synthesized logic cell
_LC3_C3 = LCELL( _EQ065);
_EQ065 = _LC4_C3 & m_state~2
# _LC4_C3 & m_state~1
# _LC5_C15 & !m_state~1 & !m_state~2;
-- Node name is '~1321~1'
-- Equation name is '~1321~1', location is LC8_C15, type is buried.
-- synthesized logic cell
_LC8_C15 = LCELL( _EQ066);
_EQ066 = !keyvalue0 & keyvalue1 & keyvalue3 & m_state~2;
-- Node name is '~1323~1'
-- Equation name is '~1323~1', location is LC7_C15, type is buried.
-- synthesized logic cell
_LC7_C15 = LCELL( _EQ067);
_EQ067 = keyvalue0 & keyvalue2 & keyvalue3 & m_state~2;
-- Node name is '~1330~1'
-- Equation name is '~1330~1', location is LC4_C15, type is buried.
-- synthesized logic cell
_LC4_C15 = LCELL( _EQ068);
_EQ068 = keyvalue0 & !keyvalue1 & keyvalue2 & keyvalue3
# !keyvalue0 & keyvalue1 & keyvalue2 & keyvalue3;
-- Node name is '~1330~2'
-- Equation name is '~1330~2', location is LC6_C3, type is buried.
-- synthesized logic cell
_LC6_C3 = LCELL( _EQ069);
_EQ069 = _LC4_C15 & !m_state~4
# !m_state~2 & !m_state~4
# _LC4_C15 & !_LC5_C15
# !_LC5_C15 & !m_state~2;
-- Node name is '~1330~3'
-- Equation name is '~1330~3', location is LC8_C3, type is buried.
-- synthesized logic cell
_LC8_C3 = LCELL( _EQ070);
_EQ070 = !m_state~1 & m_state~5
# !_LC2_C15 & m_state~5
# _LC6_C15 & !m_state~1
# !_LC2_C15 & _LC6_C15;
Project Information d:\shumaxianshi9.7\ztja.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 31,110K
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