📄 ztja.rpt
字号:
162 - - - 05 INPUT ^ 0 0 0 2 keyin16
15 - - B -- INPUT ^ 0 0 0 2 keyin17
180 - - - 18 INPUT ^ 0 0 0 2 keyin18
93 - - - 10 INPUT ^ 0 0 0 2 keyin19
144 - - B -- INPUT ^ 0 0 0 2 keyin20
164 - - - 06 INPUT ^ 0 0 0 2 keyin21
174 - - - 14 INPUT ^ 0 0 0 2 keyin22
102 - - - 03 INPUT ^ 0 0 0 2 keyin23
86 - - - 15 INPUT ^ 0 0 0 2 keyin24
88 - - - 14 INPUT ^ 0 0 0 2 keyin25
183 - - - -- INPUT ^ 0 0 0 2 keyin26
103 - - - 02 INPUT ^ 0 0 0 2 keyin27
140 - - B -- INPUT ^ 0 0 0 2 keyin28
97 - - - 07 INPUT ^ 0 0 0 2 keyin29
160 - - - 04 INPUT ^ 0 0 0 2 keyin30
184 - - - -- INPUT ^ 0 0 0 2 keyin31
19 - - C -- INPUT ^ 0 0 0 6 keyvalue0
17 - - C -- INPUT ^ 0 0 0 7 keyvalue1
18 - - C -- INPUT ^ 0 0 0 6 keyvalue2
132 - - C -- INPUT ^ 0 0 0 6 keyvalue3
78 - - - -- INPUT G ^ 0 0 0 1 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\shumaxianshi9.7\ztja.rpt
ztja
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
134 - - C -- OUTPUT 0 1 0 0 clr
133 - - C -- OUTPUT 0 1 0 0 keyout1
24 - - C -- OUTPUT 0 1 0 0 keyout2
135 - - C -- OUTPUT 0 1 0 0 keyout3
131 - - C -- OUTPUT 0 1 0 0 keyout4
136 - - C -- OUTPUT 0 1 0 0 z
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\shumaxianshi9.7\ztja.rpt
ztja
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 15 DFFE +s 1 2 1 0 m_state~1~2
- 1 - C 15 DFFE + 1 2 1 3 m_state~1
- 7 - C 03 DFFE + 0 2 1 5 m_state~2
- 2 - C 03 DFFE + 0 2 0 4 m_state~3
- 8 - C 13 DFFE + 1 2 1 1 m_state~4
- 5 - C 03 DFFE + 0 4 1 4 m_state~5
- 4 - C 03 DFFE + 1 3 1 1 :44
- 4 - B 15 DFFE + 1 1 0 1 b31 (:46)
- 5 - B 07 DFFE + 1 1 0 1 b30 (:47)
- 5 - B 15 DFFE + 1 1 0 1 b29 (:48)
- 1 - B 15 DFFE + 1 1 0 1 b28 (:49)
- 3 - B 01 DFFE + 1 1 0 1 b27 (:50)
- 2 - B 15 DFFE + 1 1 0 1 b26 (:51)
- 8 - B 15 DFFE + 1 1 0 1 b25 (:52)
- 7 - B 15 DFFE + 1 1 0 1 b24 (:53)
- 4 - B 07 DFFE + 1 1 0 1 b23 (:54)
- 3 - B 07 DFFE + 1 1 0 1 b22 (:55)
- 8 - B 13 DFFE + 1 1 0 1 b21 (:56)
- 7 - B 13 DFFE + 1 1 0 1 b20 (:57)
- 8 - B 07 DFFE + 1 1 0 1 b19 (:58)
- 6 - B 07 DFFE + 1 1 0 1 b18 (:59)
- 4 - B 01 DFFE + 1 1 0 1 b17 (:60)
- 1 - B 08 DFFE + 1 1 0 1 b16 (:61)
- 8 - B 11 DFFE + 1 1 0 1 b15 (:62)
- 5 - B 08 DFFE + 1 1 0 1 b14 (:63)
- 7 - B 08 DFFE + 1 1 0 1 b13 (:64)
- 6 - B 08 DFFE + 1 1 0 1 b12 (:65)
- 6 - B 13 DFFE + 1 1 0 1 b11 (:66)
- 4 - B 11 DFFE + 1 1 0 1 b10 (:67)
- 3 - B 14 DFFE + 1 1 0 1 b9 (:68)
- 2 - B 14 DFFE + 1 1 0 1 b8 (:69)
- 4 - B 08 DFFE + 1 1 0 1 b7 (:70)
- 2 - B 11 DFFE + 1 1 0 1 b6 (:71)
- 7 - B 11 DFFE + 1 1 0 1 b5 (:72)
- 6 - B 11 DFFE + 1 1 0 1 b4 (:73)
- 5 - B 13 DFFE + 1 1 0 1 b3 (:74)
- 2 - B 13 DFFE + 1 1 0 1 b2 (:75)
- 2 - B 01 DFFE + 1 1 0 1 b1 (:76)
- 5 - B 11 DFFE + ! 1 1 0 1 b0 (:77)
- 6 - C 15 AND2 4 0 0 2 :365
- 4 - B 14 OR2 s 2 2 0 1 ~510~1
- 2 - B 08 OR2 s 2 2 0 1 ~510~2
- 8 - B 08 OR2 s 2 2 0 1 ~510~3
- 3 - B 08 OR2 s 2 2 0 1 ~510~4
- 5 - B 14 AND2 s 0 4 0 1 ~510~5
- 1 - B 11 OR2 s 2 2 0 1 ~510~6
- 3 - B 11 OR2 s 2 2 0 1 ~510~7
- 1 - B 13 OR2 s 2 2 0 1 ~510~8
- 4 - B 13 OR2 s 2 2 0 1 ~510~9
- 6 - B 14 AND2 s 0 4 0 1 ~510~10
- 2 - B 07 OR2 s 2 2 0 1 ~510~11
- 1 - B 07 OR2 s 2 2 0 1 ~510~12
- 3 - B 15 OR2 s 2 2 0 1 ~510~13
- 7 - B 01 OR2 s 2 2 0 1 ~510~14
- 7 - B 14 AND2 s 0 4 0 1 ~510~15
- 3 - B 13 OR2 s 2 2 0 1 ~510~16
- 7 - B 07 OR2 s 2 2 0 1 ~510~17
- 1 - B 01 OR2 s 2 2 0 1 ~510~18
- 6 - B 15 OR2 s 2 2 0 1 ~510~19
- 8 - B 14 AND2 s 0 4 0 1 ~510~20
- 1 - B 14 AND2 0 4 0 2 :510
- 2 - C 15 OR2 ! 4 0 0 3 :627
- 5 - C 15 AND2 4 0 0 3 :749
- 1 - C 03 OR2 s 0 4 0 32 ~1293~1
- 3 - C 03 OR2 s 0 4 0 1 ~1310~1
- 8 - C 15 AND2 s 3 1 0 1 ~1321~1
- 7 - C 15 AND2 s 3 1 0 2 ~1323~1
- 4 - C 15 OR2 s 4 0 0 1 ~1330~1
- 6 - C 03 OR2 s 0 4 0 1 ~1330~2
- 8 - C 03 OR2 s 0 4 0 1 ~1330~3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\shumaxianshi9.7\ztja.rpt
ztja
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 33/144( 22%) 15/ 72( 20%) 0/ 72( 0%) 10/16( 62%) 0/16( 0%) 0/16( 0%)
C: 7/144( 4%) 9/ 72( 12%) 0/ 72( 0%) 4/16( 25%) 6/16( 37%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\shumaxianshi9.7\ztja.rpt
ztja
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 39 en
Device-Specific Information: d:\shumaxianshi9.7\ztja.rpt
ztja
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 39 reset
Device-Specific Information: d:\shumaxianshi9.7\ztja.rpt
ztja
** EQUATIONS **
en : INPUT;
keyin0 : INPUT;
keyin1 : INPUT;
keyin2 : INPUT;
keyin3 : INPUT;
keyin4 : INPUT;
keyin5 : INPUT;
keyin6 : INPUT;
keyin7 : INPUT;
keyin8 : INPUT;
keyin9 : INPUT;
keyin10 : INPUT;
keyin11 : INPUT;
keyin12 : INPUT;
keyin13 : INPUT;
keyin14 : INPUT;
keyin15 : INPUT;
keyin16 : INPUT;
keyin17 : INPUT;
keyin18 : INPUT;
keyin19 : INPUT;
keyin20 : INPUT;
keyin21 : INPUT;
keyin22 : INPUT;
keyin23 : INPUT;
keyin24 : INPUT;
keyin25 : INPUT;
keyin26 : INPUT;
keyin27 : INPUT;
keyin28 : INPUT;
keyin29 : INPUT;
keyin30 : INPUT;
keyin31 : INPUT;
keyvalue0 : INPUT;
keyvalue1 : INPUT;
keyvalue2 : INPUT;
keyvalue3 : INPUT;
reset : INPUT;
-- Node name is ':77' = 'b0'
-- Equation name is 'b0', location is LC5_B11, type is buried.
!b0 = b0~NOT;
b0~NOT = DFFE( _EQ001, GLOBAL( en), GLOBAL( reset), VCC, VCC);
_EQ001 = !b0 & !keyin0
# !b0 & _LC1_C3
# !keyin0 & !_LC1_C3;
-- Node name is ':76' = 'b1'
-- Equation name is 'b1', location is LC2_B1, type is buried.
b1 = DFFE( _EQ002, GLOBAL( en), GLOBAL( reset), VCC, VCC);
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