feg24b.vhd

来自「在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取」· VHDL 代码 · 共 29 行

library ieee;  
use ieee.std_logic_1164.all;  
entity feg24b is  
 port(load,reset:in std_logic;  
 din:in std_logic_vector(23 downto 0);  
 dout:out std_logic_vector(23 downto 0));  
end feg24b;  
architecture be_feg24b of feg24b is
signal q:std_logic_vector(23 downto 0);  
begin 
 dout<=q;
process(load,reset)  
begin 
   if reset='0' then
    q<=X"000000";
--m_state<=s0;
elsif load'event and load='1'  then  
  q<=din; 

  --if load'event and load='1'  then  
  --dout<=din; 
 --elsif reset='0'then
  --dout<=q;
  --end if; 
 end if;  
end process;  
end be_feg24b;