📄 mux8.rpt
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LC | | A B C D | Logic cells that feed LAB 'C':
Pin
12 -> * | - - * - | <-- d20
7 -> * | - - * - | <-- d24
30 -> * | - - * - | <-- d28
15 -> * | * - * * | <-- sel0
17 -> * | * - * * | <-- sel1
18 -> * | * - * * | <-- sel2
LC9 -> * | - - * - | <-- ~867~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\shumaxianshi\mux8.rpt
mux8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------- LC52 y1
| +--------- LC51 y2
| | +------- LC49 y3
| | | +----- LC56 ~795~1
| | | | +--- LC55 ~819~1
| | | | | +- LC54 ~843~1
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'D'
LC | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC56 -> - - * - - - | - - - * | <-- ~795~1
LC55 -> - * - - - - | - - - * | <-- ~819~1
LC54 -> * - - - - - | - - - * | <-- ~843~1
Pin
20 -> - - - - - * | - - - * | <-- d1
37 -> - - - - * - | - - - * | <-- d2
45 -> - - - * - - | - - - * | <-- d3
59 -> - - - - - * | - - - * | <-- d5
33 -> - - - - * - | - - - * | <-- d6
24 -> - - - * - - | - - - * | <-- d7
19 -> - - - - - * | - - - * | <-- d9
49 -> - - - - * - | - - - * | <-- d10
47 -> - - - * - - | - - - * | <-- d11
42 -> - - - - - * | - - - * | <-- d13
41 -> - - - - * - | - - - * | <-- d14
40 -> - - - * - - | - - - * | <-- d15
22 -> - - - - - * | - - - * | <-- d17
25 -> - - - - * - | - - - * | <-- d18
13 -> - - - * - - | - - - * | <-- d19
10 -> * - - - - - | - - - * | <-- d21
9 -> - * - - - - | - - - * | <-- d22
8 -> - - * - - - | - - - * | <-- d23
5 -> * - - - - - | - - - * | <-- d25
4 -> - * - - - - | - - - * | <-- d26
32 -> - - * - - - | - - - * | <-- d27
29 -> * - - - - - | - - - * | <-- d29
28 -> - * - - - - | - - - * | <-- d30
27 -> - - * - - - | - - - * | <-- d31
15 -> * * * * * * | * - * * | <-- sel0
17 -> * * * * * * | * - * * | <-- sel1
18 -> * * * * * * | * - * * | <-- sel2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\shumaxianshi\mux8.rpt
mux8
** EQUATIONS **
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
d8 : INPUT;
d9 : INPUT;
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d14 : INPUT;
d15 : INPUT;
d16 : INPUT;
d17 : INPUT;
d18 : INPUT;
d19 : INPUT;
d20 : INPUT;
d21 : INPUT;
d22 : INPUT;
d23 : INPUT;
d24 : INPUT;
d25 : INPUT;
d26 : INPUT;
d27 : INPUT;
d28 : INPUT;
d29 : INPUT;
d30 : INPUT;
d31 : INPUT;
sel0 : INPUT;
sel1 : INPUT;
sel2 : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', location is LC036, type is output.
y0 = LCELL( _EQ001 $ VCC);
_EQ001 = !_LC009 & _X001 & _X002 & _X003;
_X001 = EXP( d20 & !sel0 & sel1 & !sel2);
_X002 = EXP( d24 & sel0 & !sel1 & !sel2);
_X003 = EXP( d28 & !sel0 & !sel1 & !sel2);
-- Node name is 'y1'
-- Equation name is 'y1', location is LC052, type is output.
y1 = LCELL( _EQ002 $ VCC);
_EQ002 = !_LC054 & _X004 & _X005 & _X006;
_X004 = EXP( d21 & !sel0 & sel1 & !sel2);
_X005 = EXP( d25 & sel0 & !sel1 & !sel2);
_X006 = EXP( d29 & !sel0 & !sel1 & !sel2);
-- Node name is 'y2'
-- Equation name is 'y2', location is LC051, type is output.
y2 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC055 & _X007 & _X008 & _X009;
_X007 = EXP( d22 & !sel0 & sel1 & !sel2);
_X008 = EXP( d26 & sel0 & !sel1 & !sel2);
_X009 = EXP( d30 & !sel0 & !sel1 & !sel2);
-- Node name is 'y3'
-- Equation name is 'y3', location is LC049, type is output.
y3 = LCELL( _EQ004 $ VCC);
_EQ004 = !_LC056 & _X010 & _X011 & _X012;
_X010 = EXP( d23 & !sel0 & sel1 & !sel2);
_X011 = EXP( d27 & sel0 & !sel1 & !sel2);
_X012 = EXP( d31 & !sel0 & !sel1 & !sel2);
-- Node name is '~795~1'
-- Equation name is '~795~1', location is LC056, type is buried.
-- synthesized logic cell
_LC056 = LCELL( _EQ005 $ GND);
_EQ005 = d3 & sel0 & sel1 & sel2
# d7 & !sel0 & sel1 & sel2
# d11 & sel0 & !sel1 & sel2
# d19 & sel0 & sel1 & !sel2
# d15 & !sel0 & !sel1 & sel2;
-- Node name is '~819~1'
-- Equation name is '~819~1', location is LC055, type is buried.
-- synthesized logic cell
_LC055 = LCELL( _EQ006 $ GND);
_EQ006 = d2 & sel0 & sel1 & sel2
# d6 & !sel0 & sel1 & sel2
# d10 & sel0 & !sel1 & sel2
# d18 & sel0 & sel1 & !sel2
# d14 & !sel0 & !sel1 & sel2;
-- Node name is '~843~1'
-- Equation name is '~843~1', location is LC054, type is buried.
-- synthesized logic cell
_LC054 = LCELL( _EQ007 $ GND);
_EQ007 = d1 & sel0 & sel1 & sel2
# d5 & !sel0 & sel1 & sel2
# d9 & sel0 & !sel1 & sel2
# d17 & sel0 & sel1 & !sel2
# d13 & !sel0 & !sel1 & sel2;
-- Node name is '~867~1'
-- Equation name is '~867~1', location is LC009, type is buried.
-- synthesized logic cell
_LC009 = LCELL( _EQ008 $ GND);
_EQ008 = d0 & sel0 & sel1 & sel2
# d4 & !sel0 & sel1 & sel2
# d8 & sel0 & !sel1 & sel2
# d16 & sel0 & sel1 & !sel2
# d12 & !sel0 & !sel1 & sel2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\shumaxianshi\mux8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,637K
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