📄 mux8.rpt
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Project Information d:\shumaxianshi\mux8.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 09/04/2007 15:58:25
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
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megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MUX8
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mux8 EPM7064LC68-7 35 4 0 8 12 12 %
User Pins: 35 4 0
Device-Specific Information: d:\shumaxianshi\mux8.rpt
mux8
***** Logic for device 'mux8' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R
E E E E
V S S S S
C E E V E E
C R R C R R
d d d G d d I G G G G G V V C V V
2 2 2 N 2 2 N N N N N N E E I E E
2 3 4 D 5 6 T D D D D D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
d21 | 10 60 | RESERVED
VCCIO | 11 59 | d5
d20 | 12 58 | GND
d19 | 13 57 | RESERVED
d0 | 14 56 | RESERVED
sel0 | 15 55 | RESERVED
GND | 16 54 | y1
sel1 | 17 53 | VCCIO
sel2 | 18 EPM7064LC68-7 52 | y2
d9 | 19 51 | y3
d1 | 20 50 | RESERVED
VCCIO | 21 49 | d10
d17 | 22 48 | GND
d8 | 23 47 | d11
d7 | 24 46 | d4
d18 | 25 45 | d3
GND | 26 44 | d12
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
d d d d V d d G V d d G y d d d V
3 3 2 2 C 2 6 N C 1 2 N 0 1 1 1 C
1 0 9 8 C 7 D C 6 D 5 4 3 C
I I I
O N O
T
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\shumaxianshi\mux8.rpt
mux8
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 12/12(100%) 1/16( 6%) 8/36( 22%)
B: LC17 - LC32 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 1/16( 6%) 11/12( 91%) 3/16( 18%) 7/36( 19%)
D: LC49 - LC64 6/16( 37%) 4/12( 33%) 12/16( 75%) 30/36( 83%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 39/48 ( 81%)
Total logic cells used: 8/64 ( 12%)
Total shareable expanders used: 12/64 ( 18%)
Total Turbo logic cells used: 8/64 ( 12%)
Total shareable expanders not available (n/a): 4/64 ( 6%)
Average fan-in: 7.50
Total fan-in: 60
Total input pins required: 35
Total output pins required: 4
Total bidirectional pins required: 0
Total logic cells required: 8
Total flipflops required: 0
Total product terms required: 36
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 12
Synthesized logic cells: 4/ 64 ( 6%)
Device-Specific Information: d:\shumaxianshi\mux8.rpt
mux8
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
14 (5) (A) INPUT 0 0 0 0 0 0 1 d0
20 (30) (B) INPUT 0 0 0 0 0 0 1 d1
37 (35) (C) INPUT 0 0 0 0 0 0 1 d2
45 (43) (C) INPUT 0 0 0 0 0 0 1 d3
46 (44) (C) INPUT 0 0 0 0 0 0 1 d4
59 (57) (D) INPUT 0 0 0 0 0 0 1 d5
33 (17) (B) INPUT 0 0 0 0 0 0 1 d6
24 (27) (B) INPUT 0 0 0 0 0 0 1 d7
23 (28) (B) INPUT 0 0 0 0 0 0 1 d8
19 (32) (B) INPUT 0 0 0 0 0 0 1 d9
49 (46) (C) INPUT 0 0 0 0 0 0 1 d10
47 (45) (C) INPUT 0 0 0 0 0 0 1 d11
44 (41) (C) INPUT 0 0 0 0 0 0 1 d12
42 (40) (C) INPUT 0 0 0 0 0 0 1 d13
41 (38) (C) INPUT 0 0 0 0 0 0 1 d14
40 (37) (C) INPUT 0 0 0 0 0 0 1 d15
36 (33) (C) INPUT 0 0 0 0 0 0 1 d16
22 (29) (B) INPUT 0 0 0 0 0 0 1 d17
25 (25) (B) INPUT 0 0 0 0 0 0 1 d18
13 (6) (A) INPUT 0 0 0 0 0 0 1 d19
12 (8) (A) INPUT 0 0 0 0 0 1 0 d20
10 (9) (A) INPUT 0 0 0 0 0 1 0 d21
9 (11) (A) INPUT 0 0 0 0 0 1 0 d22
8 (12) (A) INPUT 0 0 0 0 0 1 0 d23
7 (13) (A) INPUT 0 0 0 0 0 1 0 d24
5 (14) (A) INPUT 0 0 0 0 0 1 0 d25
4 (16) (A) INPUT 0 0 0 0 0 1 0 d26
32 (19) (B) INPUT 0 0 0 0 0 1 0 d27
30 (20) (B) INPUT 0 0 0 0 0 1 0 d28
29 (21) (B) INPUT 0 0 0 0 0 1 0 d29
28 (22) (B) INPUT 0 0 0 0 0 1 0 d30
27 (24) (B) INPUT 0 0 0 0 0 1 0 d31
15 (4) (A) INPUT 0 0 0 0 0 4 4 sel0
17 (3) (A) INPUT 0 0 0 0 0 4 4 sel1
18 (1) (A) INPUT 0 0 0 0 0 4 4 sel2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\shumaxianshi\mux8.rpt
mux8
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
39 36 C OUTPUT t 3 0 0 6 1 0 0 y0
54 52 D OUTPUT t 3 0 0 6 1 0 0 y1
52 51 D OUTPUT t 3 0 0 6 1 0 0 y2
51 49 D OUTPUT t 3 0 0 6 1 0 0 y3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\shumaxianshi\mux8.rpt
mux8
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(57) 56 D SOFT s t 1 0 1 8 0 1 0 ~795~1
- 55 D SOFT s t 1 0 1 8 0 1 0 ~819~1
(56) 54 D SOFT s t 1 0 1 8 0 1 0 ~843~1
(10) 9 A SOFT s t 1 0 1 8 0 1 0 ~867~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\shumaxianshi\mux8.rpt
mux8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC9 ~867~1
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B C D | Logic cells that feed LAB 'A':
Pin
14 -> * | * - - - | <-- d0
46 -> * | * - - - | <-- d4
23 -> * | * - - - | <-- d8
44 -> * | * - - - | <-- d12
36 -> * | * - - - | <-- d16
15 -> * | * - * * | <-- sel0
17 -> * | * - * * | <-- sel1
18 -> * | * - * * | <-- sel2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\shumaxianshi\mux8.rpt
mux8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+- LC36 y0
|
| Other LABs fed by signals
| that feed LAB 'C'
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