store.rpt

在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

         # !keyout26 & !keyvalue1 & !keyvalue2
         # !keyout26 &  _X018;
  _X001  = EXP(!keyvalue1 & !keyvalue2);
  _X018  = EXP( keyout30 &  keyvalue3);
  _EQ066 =  _X002;
  _X002  = EXP(!clr &  reset);

-- Node name is 'keyout31' = 'a31' 
-- Equation name is 'keyout31', location is LC012, type is output.
 keyout31 = DFFE( _EQ067 $  VCC, GLOBAL( en), !_EQ068,  VCC,  VCC);
  _EQ067 = !keyvalue0 & !keyvalue1 &  keyvalue2 &  keyvalue3
         # !keyout31 &  keyvalue3 &  _X001
         # !keyout27 & !keyvalue1 & !keyvalue2
         # !keyout27 &  _X019;
  _X001  = EXP(!keyvalue1 & !keyvalue2);
  _X019  = EXP( keyout31 &  keyvalue3);
  _EQ068 =  _X002;
  _X002  = EXP(!clr &  reset);

-- Node name is '~1614~1' 
-- Equation name is '~1614~1', location is LC015, type is buried.
-- synthesized logic cell 
_LC015   = LCELL( _EQ069 $  GND);
  _EQ069 = !keyout19 & !keyout23 &  keyvalue0
         # !keyout19 & !keyvalue1 & !keyvalue2
         # !keyout19 & !keyvalue3;

-- Node name is '~1620~1' 
-- Equation name is '~1620~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ070 $  GND);
  _EQ070 = !keyout18 & !keyout22 &  keyvalue0
         # !keyout18 & !keyvalue1 & !keyvalue2
         # !keyout18 & !keyvalue3;

-- Node name is '~1626~1' 
-- Equation name is '~1626~1', location is LC044, type is buried.
-- synthesized logic cell 
_LC044   = LCELL( _EQ071 $  GND);
  _EQ071 = !keyout17 & !keyout21 &  keyvalue0
         # !keyout17 & !keyvalue1 & !keyvalue2
         # !keyout17 & !keyvalue3;

-- Node name is '~1632~1' 
-- Equation name is '~1632~1', location is LC063, type is buried.
-- synthesized logic cell 
_LC063   = LCELL( _EQ072 $  GND);
  _EQ072 = !keyout16 & !keyout20 &  keyvalue0
         # !keyout16 & !keyvalue1 & !keyvalue2
         # !keyout16 & !keyvalue3;

-- Node name is '~1638~1' 
-- Equation name is '~1638~1', location is LC045, type is buried.
-- synthesized logic cell 
_LC045   = LCELL( _EQ073 $  GND);
  _EQ073 = !keyout15 & !keyout19 &  keyvalue0
         # !keyout15 & !keyvalue1 & !keyvalue2
         # !keyout15 & !keyvalue3;

-- Node name is '~1644~1' 
-- Equation name is '~1644~1', location is LC031, type is buried.
-- synthesized logic cell 
_LC031   = LCELL( _EQ074 $  GND);
  _EQ074 = !keyout14 & !keyout18 &  keyvalue0
         # !keyout14 & !keyvalue1 & !keyvalue2
         # !keyout14 & !keyvalue3;

-- Node name is '~1650~1' 
-- Equation name is '~1650~1', location is LC046, type is buried.
-- synthesized logic cell 
_LC046   = LCELL( _EQ075 $  GND);
  _EQ075 = !keyout13 & !keyout17 &  keyvalue0
         # !keyout13 & !keyvalue1 & !keyvalue2
         # !keyout13 & !keyvalue3;

-- Node name is '~1656~1' 
-- Equation name is '~1656~1', location is LC060, type is buried.
-- synthesized logic cell 
_LC060   = LCELL( _EQ076 $  GND);
  _EQ076 = !keyout12 & !keyout16 &  keyvalue0
         # !keyout12 & !keyvalue1 & !keyvalue2
         # !keyout12 & !keyvalue3;

-- Node name is '~1662~1' 
-- Equation name is '~1662~1', location is LC032, type is buried.
-- synthesized logic cell 
_LC032   = LCELL( _EQ077 $  GND);
  _EQ077 = !keyout11 & !keyout15 &  keyvalue0
         # !keyout11 & !keyvalue1 & !keyvalue2
         # !keyout11 & !keyvalue3;

-- Node name is '~1668~1' 
-- Equation name is '~1668~1', location is LC026, type is buried.
-- synthesized logic cell 
_LC026   = LCELL( _EQ078 $  GND);
  _EQ078 = !keyout10 & !keyout14 &  keyvalue0
         # !keyout10 & !keyvalue1 & !keyvalue2
         # !keyout10 & !keyvalue3;

-- Node name is '~1674~1' 
-- Equation name is '~1674~1', location is LC042, type is buried.
-- synthesized logic cell 
_LC042   = LCELL( _EQ079 $  GND);
  _EQ079 = !keyout9 & !keyout13 &  keyvalue0
         # !keyout9 & !keyvalue1 & !keyvalue2
         # !keyout9 & !keyvalue3;

-- Node name is '~1680~1' 
-- Equation name is '~1680~1', location is LC055, type is buried.
-- synthesized logic cell 
_LC055   = LCELL( _EQ080 $  GND);
  _EQ080 = !keyout8 & !keyout12 &  keyvalue0
         # !keyout8 & !keyvalue1 & !keyvalue2
         # !keyout8 & !keyvalue3;

-- Node name is '~1686~1' 
-- Equation name is '~1686~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ081 $  GND);
  _EQ081 = !keyout7 & !keyout11 &  keyvalue0
         # !keyout7 & !keyvalue1 & !keyvalue2
         # !keyout7 & !keyvalue3;

-- Node name is '~1692~1' 
-- Equation name is '~1692~1', location is LC062, type is buried.
-- synthesized logic cell 
_LC062   = LCELL( _EQ082 $  GND);
  _EQ082 = !keyout6 & !keyout10 &  keyvalue0
         # !keyout6 & !keyvalue1 & !keyvalue2
         # !keyout6 & !keyvalue3;

-- Node name is '~1698~1' 
-- Equation name is '~1698~1', location is LC039, type is buried.
-- synthesized logic cell 
_LC039   = LCELL( _EQ083 $  GND);
  _EQ083 = !keyout5 & !keyout9 &  keyvalue0
         # !keyout5 & !keyvalue1 & !keyvalue2
         # !keyout5 & !keyvalue3;

-- Node name is '~1704~1' 
-- Equation name is '~1704~1', location is LC058, type is buried.
-- synthesized logic cell 
_LC058   = LCELL( _EQ084 $  GND);
  _EQ084 = !keyout4 & !keyout8 &  keyvalue0
         # !keyout4 & !keyvalue1 & !keyvalue2
         # !keyout4 & !keyvalue3;

-- Node name is '~1710~1' 
-- Equation name is '~1710~1', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ085 $  GND);
  _EQ085 = !keyout3 & !keyout7 &  keyvalue0
         # !keyout3 & !keyvalue1 & !keyvalue2
         # !keyout3 & !keyvalue3;

-- Node name is '~1716~1' 
-- Equation name is '~1716~1', location is LC050, type is buried.
-- synthesized logic cell 
_LC050   = LCELL( _EQ086 $  GND);
  _EQ086 = !keyout2 & !keyout6 &  keyvalue0
         # !keyout2 & !keyvalue1 & !keyvalue2
         # !keyout2 & !keyvalue3;

-- Node name is '~1722~1' 
-- Equation name is '~1722~1', location is LC034, type is buried.
-- synthesized logic cell 
_LC034   = LCELL( _EQ087 $  GND);
  _EQ087 = !keyout1 & !keyout5 &  keyvalue0
         # !keyout1 & !keyvalue1 & !keyvalue2
         # !keyout1 & !keyvalue3;

-- Node name is '~1728~1' 
-- Equation name is '~1728~1', location is LC064, type is buried.
-- synthesized logic cell 
_LC064   = LCELL( _EQ088 $  GND);
  _EQ088 = !keyout0 & !keyout4 &  keyvalue0
         # !keyout0 & !keyvalue1 & !keyvalue2
         # !keyout0 & !keyvalue3;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs A, B, C, D
--    _X002 occurs in LABs A, B, C, D




Project Information                                  d:\shumaxianshi\store.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 9,270K