📄 store.rpt
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Project Information d:\shumaxianshi\store.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 09/06/2007 14:59:37
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
STORE
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
store EPM7064LC68-7 7 32 0 52 25 81 %
User Pins: 7 32 0
Project Information d:\shumaxianshi\store.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'en' chosen for auto global Clock
Device-Specific Information: d:\shumaxianshi\store.rpt
store
***** Logic for device 'store' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
k k R k R R R k R
e e E e E E E e E
y y S y S V S S y S
o o E o E C E E V o E
u u R u R C R R C u R
t t V G t V I G G G G V V C t V
2 3 E N 2 E N N N N e N E E I 2 E
3 1 D D 7 D T D D D n D D D O 4 D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
keyout19 | 10 60 | keyout28
VCCIO | 11 59 | keyout12
keyvalue1 | 12 58 | GND
keyvalue2 | 13 57 | keyout16
keyvalue3 | 14 56 | keyout20
reset | 15 55 | keyout4
GND | 16 54 | keyout0
keyvalue0 | 17 53 | VCCIO
clr | 18 EPM7064LC68-7 52 | keyout2
RESERVED | 19 51 | keyout8
keyout26 | 20 50 | keyout13
VCCIO | 21 49 | RESERVED
RESERVED | 22 48 | GND
keyout30 | 23 47 | RESERVED
keyout14 | 24 46 | RESERVED
keyout18 | 25 45 | keyout17
GND | 26 44 | keyout25
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
k k k k V k k G V k k G k k k k V
e e e e C e e N C e e N e e e e C
y y y y C y y D C y y D y y y y C
o o o o I o o I o o o o o o I
u u u u O u u N u u u u u u O
t t t t t t T t t t t t t
2 3 1 7 6 1 2 1 9 5 1 2
2 1 0 9 5 1
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\shumaxianshi\store.rpt
store
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 5/16( 31%) 10/12( 83%) 10/16( 62%) 12/36( 33%)
B: LC17 - LC32 16/16(100%) 10/12( 83%) 16/16(100%) 24/36( 66%)
C: LC33 - LC48 15/16( 93%) 9/12( 75%) 15/16( 93%) 22/36( 61%)
D: LC49 - LC64 16/16(100%) 9/12( 75%) 16/16(100%) 22/36( 61%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 38/48 ( 79%)
Total logic cells used: 52/64 ( 81%)
Total shareable expanders used: 25/64 ( 39%)
Total Turbo logic cells used: 52/64 ( 81%)
Total shareable expanders not available (n/a): 32/64 ( 50%)
Average fan-in: 8.30
Total fan-in: 432
Total input pins required: 7
Total output pins required: 32
Total bidirectional pins required: 0
Total logic cells required: 52
Total flipflops required: 32
Total product terms required: 245
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 19
Synthesized logic cells: 20/ 64 ( 31%)
Device-Specific Information: d:\shumaxianshi\store.rpt
store
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
18 (1) (A) INPUT 0 0 0 0 0 32 0 clr
67 - - INPUT G 0 0 0 0 0 0 0 en
17 (3) (A) INPUT 0 0 0 0 0 32 20 keyvalue0
12 (8) (A) INPUT 0 0 0 0 0 32 20 keyvalue1
13 (6) (A) INPUT 0 0 0 0 0 32 20 keyvalue2
14 (5) (A) INPUT 0 0 0 0 0 32 20 keyvalue3
15 (4) (A) INPUT 0 0 0 0 0 32 0 reset
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\shumaxianshi\store.rpt
store
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
54 52 D FF + t 3 2 1 6 2 1 1 keyout0 (:71)
41 38 C FF + t 2 1 1 6 2 1 1 keyout1 (:70)
52 51 D FF + t 3 1 1 6 2 1 1 keyout2 (:69)
28 22 B FF + t 2 1 1 6 2 1 1 keyout3 (:68)
55 53 D FF + t 2 1 1 6 3 2 2 keyout4 (:67)
40 37 C FF + t 2 1 1 6 3 2 2 keyout5 (:66)
32 19 B FF + t 2 1 1 6 3 2 2 keyout6 (:65)
30 20 B FF + t 2 1 1 6 3 2 2 keyout7 (:64)
51 49 D FF + t 2 1 1 6 3 2 2 keyout8 (:63)
39 36 C FF + t 2 1 1 6 3 2 2 keyout9 (:62)
33 17 B FF + t 2 1 1 6 3 2 2 keyout10 (:61)
29 21 B FF + t 2 1 1 6 3 2 2 keyout11 (:60)
59 57 D FF + t 2 1 1 6 3 2 2 keyout12 (:59)
50 48 C FF + t 2 1 1 6 3 2 2 keyout13 (:58)
24 27 B FF + t 2 1 1 6 3 2 2 keyout14 (:57)
37 35 C FF + t 2 1 1 6 3 2 2 keyout15 (:56)
57 56 D FF + t 2 1 1 6 3 2 2 keyout16 (:55)
45 43 C FF + t 2 1 1 6 3 2 2 keyout17 (:54)
25 25 B FF + t 2 1 1 6 3 2 2 keyout18 (:53)
10 9 A FF + t 2 1 1 6 3 2 2 keyout19 (:52)
56 54 D FF + t 2 1 1 6 3 3 1 keyout20 (:51)
42 40 C FF + t 2 1 1 6 3 3 1 keyout21 (:50)
27 24 B FF + t 2 1 1 6 3 3 1 keyout22 (:49)
9 11 A FF + t 2 1 1 6 3 3 1 keyout23 (:48)
62 61 D FF + t 5 1 1 6 3 3 0 keyout24 (:47)
44 41 C FF + t 5 1 1 6 3 3 0 keyout25 (:46)
20 30 B FF + t 5 1 1 6 3 3 0 keyout26 (:45)
5 14 A FF + t 5 1 1 6 3 3 0 keyout27 (:44)
60 59 D FF + t 4 2 1 6 2 2 0 keyout28 (:43)
36 33 C FF + t 4 2 1 6 2 2 0 keyout29 (:42)
23 28 B FF + t 4 2 1 6 2 2 0 keyout30 (:41)
8 12 A FF + t 4 2 1 6 2 2 0 keyout31 (:40)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\shumaxianshi\store.rpt
store
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 15 A SOFT s t 0 0 0 4 2 1 0 ~1614~1
- 18 B SOFT s t 0 0 0 4 2 1 0 ~1620~1
(46) 44 C SOFT s t 0 0 0 4 2 1 0 ~1626~1
- 63 D SOFT s t 0 0 0 4 2 1 0 ~1632~1
(47) 45 C SOFT s t 0 0 0 4 2 1 0 ~1638~1
- 31 B SOFT s t 0 0 0 4 2 1 0 ~1644~1
(49) 46 C SOFT s t 0 0 0 4 2 1 0 ~1650~1
(61) 60 D SOFT s t 0 0 0 4 2 1 0 ~1656~1
(19) 32 B SOFT s t 0 0 0 4 2 1 0 ~1662~1
- 26 B SOFT s t 0 0 0 4 2 1 0 ~1668~1
- 42 C SOFT s t 0 0 0 4 2 1 0 ~1674~1
- 55 D SOFT s t 0 0 0 4 2 1 0 ~1680~1
- 23 B SOFT s t 0 0 0 4 2 1 0 ~1686~1
(64) 62 D SOFT s t 0 0 0 4 2 1 0 ~1692~1
- 39 C SOFT s t 0 0 0 4 2 1 0 ~1698~1
- 58 D SOFT s t 0 0 0 4 2 1 0 ~1704~1
(22) 29 B SOFT s t 0 0 0 4 2 1 0 ~1710~1
- 50 D SOFT s t 0 0 0 4 2 1 0 ~1716~1
- 34 C SOFT s t 0 0 0 4 2 1 0 ~1722~1
(65) 64 D SOFT s t 0 0 0 4 2 1 0 ~1728~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\shumaxianshi\store.rpt
store
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
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