feg24b.rpt

在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

9    -> - - - - - - - - - * - - | - - * - | <-- din21
8    -> - - - - - - - - - - * - | - - * - | <-- din22
7    -> - - - - - - - - - - - * | - - * - | <-- din23
67   -> - - - - - - - - - - - - | - - - - | <-- load
18   -> * * * * * * * * * * * * | - - * * | <-- reset


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                     d:\shumaxianshi9.7\feg24b.rpt
feg24b

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                 Logic cells placed in LAB 'D'
        +----------------------- LC64 dout0
        | +--------------------- LC59 dout1
        | | +------------------- LC56 dout2
        | | | +----------------- LC54 dout3
        | | | | +--------------- LC60 dout4
        | | | | | +------------- LC61 dout5
        | | | | | | +----------- LC52 dout6
        | | | | | | | +--------- LC62 dout7
        | | | | | | | | +------- LC57 dout8
        | | | | | | | | | +----- LC53 dout9
        | | | | | | | | | | +--- LC51 dout10
        | | | | | | | | | | | +- LC49 dout11
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':

Pin
5    -> * - - - - - - - - - - - | - - - * | <-- din0
28   -> - * - - - - - - - - - - | - - - * | <-- din1
29   -> - - * - - - - - - - - - | - - - * | <-- din2
27   -> - - - * - - - - - - - - | - - - * | <-- din3
25   -> - - - - * - - - - - - - | - - - * | <-- din4
22   -> - - - - - * - - - - - - | - - - * | <-- din5
20   -> - - - - - - * - - - - - | - - - * | <-- din6
24   -> - - - - - - - * - - - - | - - - * | <-- din7
23   -> - - - - - - - - * - - - | - - - * | <-- din8
19   -> - - - - - - - - - * - - | - - - * | <-- din9
68   -> - - - - - - - - - - * - | - - - * | <-- din10
33   -> - - - - - - - - - - - * | - - - * | <-- din11
67   -> - - - - - - - - - - - - | - - - - | <-- load
18   -> * * * * * * * * * * * * | - - * * | <-- reset


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                     d:\shumaxianshi9.7\feg24b.rpt
feg24b

** EQUATIONS **

din0     : INPUT;
din1     : INPUT;
din2     : INPUT;
din3     : INPUT;
din4     : INPUT;
din5     : INPUT;
din6     : INPUT;
din7     : INPUT;
din8     : INPUT;
din9     : INPUT;
din10    : INPUT;
din11    : INPUT;
din12    : INPUT;
din13    : INPUT;
din14    : INPUT;
din15    : INPUT;
din16    : INPUT;
din17    : INPUT;
din18    : INPUT;
din19    : INPUT;
din20    : INPUT;
din21    : INPUT;
din22    : INPUT;
din23    : INPUT;
load     : INPUT;
reset    : INPUT;

-- Node name is 'dout0' = 'q0' 
-- Equation name is 'dout0', location is LC064, type is output.
 dout0   = DFFE( din0 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout1' = 'q1' 
-- Equation name is 'dout1', location is LC059, type is output.
 dout1   = DFFE( din1 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout2' = 'q2' 
-- Equation name is 'dout2', location is LC056, type is output.
 dout2   = DFFE( din2 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout3' = 'q3' 
-- Equation name is 'dout3', location is LC054, type is output.
 dout3   = DFFE( din3 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout4' = 'q4' 
-- Equation name is 'dout4', location is LC060, type is output.
 dout4   = DFFE( din4 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout5' = 'q5' 
-- Equation name is 'dout5', location is LC061, type is output.
 dout5   = DFFE( din5 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout6' = 'q6' 
-- Equation name is 'dout6', location is LC052, type is output.
 dout6   = DFFE( din6 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout7' = 'q7' 
-- Equation name is 'dout7', location is LC062, type is output.
 dout7   = DFFE( din7 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout8' = 'q8' 
-- Equation name is 'dout8', location is LC057, type is output.
 dout8   = DFFE( din8 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout9' = 'q9' 
-- Equation name is 'dout9', location is LC053, type is output.
 dout9   = DFFE( din9 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout10' = 'q10' 
-- Equation name is 'dout10', location is LC051, type is output.
 dout10  = DFFE( din10 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout11' = 'q11' 
-- Equation name is 'dout11', location is LC049, type is output.
 dout11  = DFFE( din11 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout12' = 'q12' 
-- Equation name is 'dout12', location is LC037, type is output.
 dout12  = DFFE( din12 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout13' = 'q13' 
-- Equation name is 'dout13', location is LC036, type is output.
 dout13  = DFFE( din13 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout14' = 'q14' 
-- Equation name is 'dout14', location is LC033, type is output.
 dout14  = DFFE( din14 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout15' = 'q15' 
-- Equation name is 'dout15', location is LC038, type is output.
 dout15  = DFFE( din15 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout16' = 'q16' 
-- Equation name is 'dout16', location is LC040, type is output.
 dout16  = DFFE( din16 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout17' = 'q17' 
-- Equation name is 'dout17', location is LC041, type is output.
 dout17  = DFFE( din17 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout18' = 'q18' 
-- Equation name is 'dout18', location is LC045, type is output.
 dout18  = DFFE( din18 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout19' = 'q19' 
-- Equation name is 'dout19', location is LC046, type is output.
 dout19  = DFFE( din19 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout20' = 'q20' 
-- Equation name is 'dout20', location is LC048, type is output.
 dout20  = DFFE( din20 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout21' = 'q21' 
-- Equation name is 'dout21', location is LC035, type is output.
 dout21  = DFFE( din21 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout22' = 'q22' 
-- Equation name is 'dout22', location is LC043, type is output.
 dout22  = DFFE( din22 $  GND, GLOBAL( load), !reset,  VCC,  VCC);

-- Node name is 'dout23' = 'q23' 
-- Equation name is 'dout23', location is LC044, type is output.
 dout23  = DFFE( din23 $  GND, GLOBAL( load), !reset,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                              d:\shumaxianshi9.7\feg24b.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,556K