📄 feg24b.rpt
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Project Information d:\shumaxianshi9.7\feg24b.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 09/07/2007 15:20:18
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
FEG24B
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
feg24b EPM7064LC68-7 26 24 0 24 0 37 %
User Pins: 26 24 0
Project Information d:\shumaxianshi9.7\feg24b.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'load' chosen for auto global Clock
Device-Specific Information: d:\shumaxianshi9.7\feg24b.rpt
feg24b
***** Logic for device 'feg24b' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: d:\shumaxianshi9.7\feg24b.rpt
feg24b
** ERROR SUMMARY **
Info: Chip 'feg24b' in device 'EPM7064LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
V
d d d d C d d d V d d
i i i d i C i l o o C o o
n n n G i n I G G n o G u u C u u
2 2 2 N n 1 N N N 1 a N t t I t t
1 2 3 D 0 4 T D D 0 d D 0 7 O 5 4
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
din20 | 10 60 | dout1
VCCIO | 11 59 | dout8
din19 | 12 58 | GND
din18 | 13 57 | dout2
din17 | 14 56 | dout3
din16 | 15 55 | dout9
GND | 16 54 | dout6
din15 | 17 53 | VCCIO
reset | 18 EPM7064LC68-7 52 | dout10
din9 | 19 51 | dout11
din6 | 20 50 | dout20
VCCIO | 21 49 | dout19
din5 | 22 48 | GND
din8 | 23 47 | dout18
din7 | 24 46 | dout23
din4 | 25 45 | dout22
GND | 26 44 | dout17
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
d d d d V d d G V d d G d d d d V
i i i i C i i N C o o N o o o o C
n n n n C n n D C u u D u u u u C
3 1 2 1 I 1 1 I t t t t t t I
2 O 3 1 N 1 2 1 1 1 1 O
T 4 1 3 2 5 6
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\shumaxianshi9.7\feg24b.rpt
feg24b
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 12/16( 75%) 12/12(100%) 0/16( 0%) 13/36( 36%)
D: LC49 - LC64 12/16( 75%) 12/12(100%) 0/16( 0%) 13/36( 36%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 48/48 (100%)
Total logic cells used: 24/64 ( 37%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 24/64 ( 37%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 3.00
Total fan-in: 72
Total input pins required: 26
Total output pins required: 24
Total bidirectional pins required: 0
Total logic cells required: 24
Total flipflops required: 24
Total product terms required: 48
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: d:\shumaxianshi9.7\feg24b.rpt
feg24b
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
5 (14) (A) INPUT 0 0 0 0 0 1 0 din0
28 (22) (B) INPUT 0 0 0 0 0 1 0 din1
29 (21) (B) INPUT 0 0 0 0 0 1 0 din2
27 (24) (B) INPUT 0 0 0 0 0 1 0 din3
25 (25) (B) INPUT 0 0 0 0 0 1 0 din4
22 (29) (B) INPUT 0 0 0 0 0 1 0 din5
20 (30) (B) INPUT 0 0 0 0 0 1 0 din6
24 (27) (B) INPUT 0 0 0 0 0 1 0 din7
23 (28) (B) INPUT 0 0 0 0 0 1 0 din8
19 (32) (B) INPUT 0 0 0 0 0 1 0 din9
68 - - INPUT 0 0 0 0 0 1 0 din10
33 (17) (B) INPUT 0 0 0 0 0 1 0 din11
30 (20) (B) INPUT 0 0 0 0 0 1 0 din12
32 (19) (B) INPUT 0 0 0 0 0 1 0 din13
4 (16) (A) INPUT 0 0 0 0 0 1 0 din14
17 (3) (A) INPUT 0 0 0 0 0 1 0 din15
15 (4) (A) INPUT 0 0 0 0 0 1 0 din16
14 (5) (A) INPUT 0 0 0 0 0 1 0 din17
13 (6) (A) INPUT 0 0 0 0 0 1 0 din18
12 (8) (A) INPUT 0 0 0 0 0 1 0 din19
10 (9) (A) INPUT 0 0 0 0 0 1 0 din20
9 (11) (A) INPUT 0 0 0 0 0 1 0 din21
8 (12) (A) INPUT 0 0 0 0 0 1 0 din22
7 (13) (A) INPUT 0 0 0 0 0 1 0 din23
67 - - INPUT G 0 0 0 0 0 0 0 load
18 (1) (A) INPUT 0 0 0 0 0 24 0 reset
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\shumaxianshi9.7\feg24b.rpt
feg24b
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
65 64 D FF + t 0 0 0 2 0 0 0 dout0 (:74)
60 59 D FF + t 0 0 0 2 0 0 0 dout1 (:73)
57 56 D FF + t 0 0 0 2 0 0 0 dout2 (:72)
56 54 D FF + t 0 0 0 2 0 0 0 dout3 (:71)
61 60 D FF + t 0 0 0 2 0 0 0 dout4 (:70)
62 61 D FF + t 0 0 0 2 0 0 0 dout5 (:69)
54 52 D FF + t 0 0 0 2 0 0 0 dout6 (:68)
64 62 D FF + t 0 0 0 2 0 0 0 dout7 (:67)
59 57 D FF + t 0 0 0 2 0 0 0 dout8 (:66)
55 53 D FF + t 0 0 0 2 0 0 0 dout9 (:65)
52 51 D FF + t 0 0 0 2 0 0 0 dout10 (:64)
51 49 D FF + t 0 0 0 2 0 0 0 dout11 (:63)
40 37 C FF + t 0 0 0 2 0 0 0 dout12 (:62)
39 36 C FF + t 0 0 0 2 0 0 0 dout13 (:61)
36 33 C FF + t 0 0 0 2 0 0 0 dout14 (:60)
41 38 C FF + t 0 0 0 2 0 0 0 dout15 (:59)
42 40 C FF + t 0 0 0 2 0 0 0 dout16 (:58)
44 41 C FF + t 0 0 0 2 0 0 0 dout17 (:57)
47 45 C FF + t 0 0 0 2 0 0 0 dout18 (:56)
49 46 C FF + t 0 0 0 2 0 0 0 dout19 (:55)
50 48 C FF + t 0 0 0 2 0 0 0 dout20 (:54)
37 35 C FF + t 0 0 0 2 0 0 0 dout21 (:53)
45 43 C FF + t 0 0 0 2 0 0 0 dout22 (:52)
46 44 C FF + t 0 0 0 2 0 0 0 dout23 (:51)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\shumaxianshi9.7\feg24b.rpt
feg24b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------- LC37 dout12
| +--------------------- LC36 dout13
| | +------------------- LC33 dout14
| | | +----------------- LC38 dout15
| | | | +--------------- LC40 dout16
| | | | | +------------- LC41 dout17
| | | | | | +----------- LC45 dout18
| | | | | | | +--------- LC46 dout19
| | | | | | | | +------- LC48 dout20
| | | | | | | | | +----- LC35 dout21
| | | | | | | | | | +--- LC43 dout22
| | | | | | | | | | | +- LC44 dout23
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
68 -> - - - - - - - - - - - - | - - - * | <-- din10
30 -> * - - - - - - - - - - - | - - * - | <-- din12
32 -> - * - - - - - - - - - - | - - * - | <-- din13
4 -> - - * - - - - - - - - - | - - * - | <-- din14
17 -> - - - * - - - - - - - - | - - * - | <-- din15
15 -> - - - - * - - - - - - - | - - * - | <-- din16
14 -> - - - - - * - - - - - - | - - * - | <-- din17
13 -> - - - - - - * - - - - - | - - * - | <-- din18
12 -> - - - - - - - * - - - - | - - * - | <-- din19
10 -> - - - - - - - - * - - - | - - * - | <-- din20
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