testctl.vhd

在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

library ieee;  
use ieee.std_logic_1164.all;  
use ieee.std_logic_unsigned.all; 
 
entity testctl is  
 port(clk,rst:in std_logic;  
 tsten,clr_cnt,load:out std_logic);  
end testctl;
  
architecture be_testctl of testctl is  
signal div2clk:std_logic;  
begin  
process(clk)  
begin 
  --if z='1' then
  if clk'event and clk='1' then
 div2clk<=NOT div2clk;  
end if;
 

end process;  
process(clk,div2clk)  
begin 
--if z='1' then
	if clk='0' and div2clk='0' then  
      clr_cnt<='1';  
     else clr_cnt<='0';  
    end if;
    if div2clk='0'then
      load<= NOT clk;
    end if;
--els  
end process; 
tsten<=div2clk;   
--load<= NOT div2clk; 
end be_testctl;