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-- Node name is '|CNT10:7|:13' = '|CNT10:7|cq10'
-- Equation name is '_LC4_C16', type is buried
_LC4_C16 = DFFE( _EQ033, _LC7_C4, !_LC6_C2, VCC, VCC);
_EQ033 = !_LC2_C2 & _LC4_C16
# _LC2_C2 & !_LC4_C16;
-- Node name is '|CNT10:7|:12' = '|CNT10:7|cq11'
-- Equation name is '_LC3_C16', type is buried
_LC3_C16 = DFFE( _EQ034, _LC7_C4, !_LC6_C2, VCC, VCC);
_EQ034 = _LC3_C16 & !_LC4_C16 & !_LC6_C16
# _LC2_C2 & !_LC3_C16 & _LC4_C16 & !_LC6_C16
# !_LC2_C2 & _LC3_C16;
-- Node name is '|CNT10:7|:11' = '|CNT10:7|cq12'
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = DFFE( _EQ035, _LC7_C4, !_LC6_C2, VCC, VCC);
_EQ035 = _LC1_C16 & !_LC5_C16 & !_LC6_C16
# !_LC1_C16 & _LC2_C2 & _LC5_C16 & !_LC6_C16
# _LC1_C16 & !_LC2_C2;
-- Node name is '|CNT10:7|:10' = '|CNT10:7|cq13'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = DFFE( _EQ036, _LC7_C4, !_LC6_C2, VCC, VCC);
_EQ036 = _LC2_C2 & !_LC6_C16 & _LC7_C16
# !_LC2_C2 & _LC8_C16;
-- Node name is '|CNT10:7|LPM_ADD_SUB:78|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C16', type is buried
_LC5_C16 = LCELL( _EQ037);
_EQ037 = _LC3_C16 & _LC4_C16;
-- Node name is '|CNT10:7|LPM_ADD_SUB:78|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C16', type is buried
_LC7_C16 = LCELL( _EQ038);
_EQ038 = !_LC3_C16 & _LC8_C16
# !_LC4_C16 & _LC8_C16
# !_LC1_C16 & _LC8_C16
# _LC1_C16 & _LC3_C16 & _LC4_C16 & !_LC8_C16;
-- Node name is '|CNT10:7|:8'
-- Equation name is '_LC5_C11', type is buried
_LC5_C11 = DFFE( _EQ039, _LC7_C4, VCC, VCC, !_LC6_C2);
_EQ039 = _LC2_C2 & _LC6_C16
# !_LC2_C2 & _LC5_C11;
-- Node name is '|CNT10:7|:51'
-- Equation name is '_LC6_C16', type is buried
_LC6_C16 = LCELL( _EQ040);
_EQ040 = !_LC1_C16 & !_LC3_C16 & _LC4_C16 & _LC8_C16;
-- Node name is '|CNT10:8|:13' = '|CNT10:8|cq10'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = DFFE( _EQ041, _LC5_C11, !_LC6_C2, VCC, VCC);
_EQ041 = !_LC2_C2 & _LC3_C11
# _LC2_C2 & !_LC3_C11;
-- Node name is '|CNT10:8|:12' = '|CNT10:8|cq11'
-- Equation name is '_LC4_C11', type is buried
_LC4_C11 = DFFE( _EQ042, _LC5_C11, !_LC6_C2, VCC, VCC);
_EQ042 = !_LC3_C11 & _LC4_C11 & !_LC6_C11
# _LC2_C2 & _LC3_C11 & !_LC4_C11 & !_LC6_C11
# !_LC2_C2 & _LC4_C11;
-- Node name is '|CNT10:8|:11' = '|CNT10:8|cq12'
-- Equation name is '_LC2_C11', type is buried
_LC2_C11 = DFFE( _EQ043, _LC5_C11, !_LC6_C2, VCC, VCC);
_EQ043 = _LC2_C11 & !_LC6_C11 & !_LC7_C11
# _LC2_C2 & !_LC2_C11 & !_LC6_C11 & _LC7_C11
# !_LC2_C2 & _LC2_C11;
-- Node name is '|CNT10:8|:10' = '|CNT10:8|cq13'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = DFFE( _EQ044, _LC5_C11, !_LC6_C2, VCC, VCC);
_EQ044 = _LC2_C2 & !_LC6_C11 & _LC8_C11
# _LC1_C11 & !_LC2_C2;
-- Node name is '|CNT10:8|LPM_ADD_SUB:78|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = LCELL( _EQ045);
_EQ045 = _LC3_C11 & _LC4_C11;
-- Node name is '|CNT10:8|LPM_ADD_SUB:78|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_C11', type is buried
_LC8_C11 = LCELL( _EQ046);
_EQ046 = _LC1_C11 & !_LC4_C11
# _LC1_C11 & !_LC3_C11
# _LC1_C11 & !_LC2_C11
# !_LC1_C11 & _LC2_C11 & _LC3_C11 & _LC4_C11;
-- Node name is '|CNT10:8|:51'
-- Equation name is '_LC6_C11', type is buried
!_LC6_C11 = _LC6_C11~NOT;
_LC6_C11~NOT = LCELL( _EQ047);
_EQ047 = !_LC1_C11
# _LC2_C11
# _LC4_C11
# !_LC3_C11;
-- Node name is '|FEG24B:2|:74' = '|FEG24B:2|q0'
-- Equation name is '_LC3_C2', type is buried
_LC3_C2 = DFFE( _LC5_C6, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:73' = '|FEG24B:2|q1'
-- Equation name is '_LC1_C14', type is buried
_LC1_C14 = DFFE( _LC3_C6, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:72' = '|FEG24B:2|q2'
-- Equation name is '_LC8_C3', type is buried
_LC8_C3 = DFFE( _LC2_C6, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:71' = '|FEG24B:2|q3'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = DFFE( _LC1_C6, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:70' = '|FEG24B:2|q4'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = DFFE( _LC3_C17, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:69' = '|FEG24B:2|q5'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = DFFE( _LC5_C17, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:68' = '|FEG24B:2|q6'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = DFFE( _LC2_C17, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:67' = '|FEG24B:2|q7'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = DFFE( _LC1_C17, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:66' = '|FEG24B:2|q8'
-- Equation name is '_LC7_C12', type is buried
_LC7_C12 = DFFE( _LC4_C8, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:65' = '|FEG24B:2|q9'
-- Equation name is '_LC6_C3', type is buried
_LC6_C3 = DFFE( _LC3_C8, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:64' = '|FEG24B:2|q10'
-- Equation name is '_LC5_C7', type is buried
_LC5_C7 = DFFE( _LC2_C8, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:63' = '|FEG24B:2|q11'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = DFFE( _LC1_C8, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:62' = '|FEG24B:2|q12'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = DFFE( _LC4_C4, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:61' = '|FEG24B:2|q13'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = DFFE( _LC3_C4, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:60' = '|FEG24B:2|q14'
-- Equation name is '_LC8_C7', type is buried
_LC8_C7 = DFFE( _LC2_C4, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:59' = '|FEG24B:2|q15'
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = DFFE( _LC1_C4, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:58' = '|FEG24B:2|q16'
-- Equation name is '_LC8_C2', type is buried
_LC8_C2 = DFFE( _LC4_C16, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:57' = '|FEG24B:2|q17'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = DFFE( _LC3_C16, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:56' = '|FEG24B:2|q18'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = DFFE( _LC1_C16, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:55' = '|FEG24B:2|q19'
-- Equation name is '_LC2_C16', type is buried
_LC2_C16 = DFFE( _LC8_C16, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:54' = '|FEG24B:2|q20'
-- Equation name is '_LC4_C3', type is buried
_LC4_C3 = DFFE( _LC3_C11, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:53' = '|FEG24B:2|q21'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = DFFE( _LC4_C11, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:52' = '|FEG24B:2|q22'
-- Equation name is '_LC6_C7', type is buried
_LC6_C7 = DFFE( _LC2_C11, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|FEG24B:2|:51' = '|FEG24B:2|q23'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = DFFE( _LC1_C11, _LC1_C2, !reset, VCC, VCC);
-- Node name is '|TESTCTL:3|:6' = '|TESTCTL:3|div2clk'
-- Equation name is '_LC2_C2', type is buried
_LC2_C2 = DFFE(!_LC2_C2, CLK, VCC, VCC, VCC);
-- Node name is '|TESTCTL:3|:39'
-- Equation name is '_LC6_C2', type is buried
!_LC6_C2 = _LC6_C2~NOT;
_LC6_C2~NOT = LCELL( _EQ048);
_EQ048 = CLK
# _LC2_C2;
-- Node name is '|TESTCTL:3|:73'
-- Equation name is '_LC1_C2', type is buried
_LC1_C2 = LCELL( _EQ049);
_EQ049 = !CLK & !_LC2_C2
# _LC1_C2 & _LC2_C2;
Project Information d:\shumaxianshi9.7\szplj\szpljt.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,496K
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