📄 szpljt.rpt
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Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 8 6 8 0 8 4 8 0 0 8 6 1 1 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 74/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 6 8 0 8 4 8 0 0 8 6 1 1 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 74/0
Device-Specific Information: d:\shumaxianshi9.7\szplj\szpljt.rpt
szpljt
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - A -- INPUT ^ 0 0 0 3 CLK
183 - - - -- INPUT G ^ 0 0 0 0 FSIN
46 - - F -- INPUT ^ 0 0 0 24 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\shumaxianshi9.7\szplj\szpljt.rpt
szpljt
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
127 - - D -- OUTPUT 0 1 0 0 DOUT0
128 - - D -- OUTPUT 0 1 0 0 DOUT1
131 - - C -- OUTPUT 0 1 0 0 DOUT2
132 - - C -- OUTPUT 0 1 0 0 DOUT3
133 - - C -- OUTPUT 0 1 0 0 DOUT4
134 - - C -- OUTPUT 0 1 0 0 DOUT5
135 - - C -- OUTPUT 0 1 0 0 DOUT6
136 - - C -- OUTPUT 0 1 0 0 DOUT7
139 - - B -- OUTPUT 0 1 0 0 DOUT8
140 - - B -- OUTPUT 0 1 0 0 DOUT9
141 - - B -- OUTPUT 0 1 0 0 DOUT10
142 - - B -- OUTPUT 0 1 0 0 DOUT11
143 - - B -- OUTPUT 0 1 0 0 DOUT12
144 - - B -- OUTPUT 0 1 0 0 DOUT13
147 - - A -- OUTPUT 0 1 0 0 DOUT14
148 - - A -- OUTPUT 0 1 0 0 DOUT15
120 - - E -- OUTPUT 0 1 0 0 DOUT16
119 - - E -- OUTPUT 0 1 0 0 DOUT17
116 - - F -- OUTPUT 0 1 0 0 DOUT18
115 - - F -- OUTPUT 0 1 0 0 DOUT19
114 - - F -- OUTPUT 0 1 0 0 DOUT20
113 - - F -- OUTPUT 0 1 0 0 DOUT21
112 - - F -- OUTPUT 0 1 0 0 DOUT22
111 - - F -- OUTPUT 0 1 0 0 DOUT23
94 - - - 09 OUTPUT 0 0 0 0 IO_DS1
95 - - - 09 OUTPUT 0 0 0 0 IO_DS2
96 - - - 08 OUTPUT 0 0 0 0 IO_DS3
97 - - - 07 OUTPUT 0 0 0 0 IO_DS4
99 - - - 06 OUTPUT 0 0 0 0 IO_DS5
100 - - - 05 OUTPUT 0 0 0 0 IO_DS6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\shumaxianshi9.7\szplj\szpljt.rpt
szpljt
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 06 AND2 0 2 0 1 |CNT10:1|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - C 06 OR2 0 4 0 1 |CNT10:1|LPM_ADD_SUB:78|addcore:adder|:69
- 4 - C 06 DFFE + 0 3 0 5 |CNT10:1|:8
- 1 - C 06 DFFE + 0 4 0 3 |CNT10:1|cq13 (|CNT10:1|:10)
- 2 - C 06 DFFE + 0 4 0 3 |CNT10:1|cq12 (|CNT10:1|:11)
- 3 - C 06 DFFE + 0 4 0 4 |CNT10:1|cq11 (|CNT10:1|:12)
- 5 - C 06 DFFE + 0 2 0 5 |CNT10:1|cq10 (|CNT10:1|:13)
- 6 - C 06 AND2 0 4 0 4 |CNT10:1|:51
- 7 - C 17 AND2 0 2 0 1 |CNT10:4|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - C 17 OR2 0 4 0 1 |CNT10:4|LPM_ADD_SUB:78|addcore:adder|:69
- 4 - C 17 DFFE 0 4 0 5 |CNT10:4|:8
- 1 - C 17 DFFE 0 5 0 3 |CNT10:4|cq13 (|CNT10:4|:10)
- 2 - C 17 DFFE 0 5 0 3 |CNT10:4|cq12 (|CNT10:4|:11)
- 5 - C 17 DFFE 0 5 0 4 |CNT10:4|cq11 (|CNT10:4|:12)
- 3 - C 17 DFFE 0 3 0 5 |CNT10:4|cq10 (|CNT10:4|:13)
- 6 - C 17 AND2 0 4 0 4 |CNT10:4|:51
- 7 - C 08 AND2 0 2 0 1 |CNT10:5|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - C 08 OR2 0 4 0 1 |CNT10:5|LPM_ADD_SUB:78|addcore:adder|:69
- 5 - C 08 DFFE 0 4 0 5 |CNT10:5|:8
- 1 - C 08 DFFE 0 5 0 3 |CNT10:5|cq13 (|CNT10:5|:10)
- 2 - C 08 DFFE 0 5 0 3 |CNT10:5|cq12 (|CNT10:5|:11)
- 3 - C 08 DFFE 0 5 0 4 |CNT10:5|cq11 (|CNT10:5|:12)
- 4 - C 08 DFFE 0 3 0 5 |CNT10:5|cq10 (|CNT10:5|:13)
- 6 - C 08 AND2 0 4 0 4 |CNT10:5|:51
- 6 - C 04 AND2 0 2 0 1 |CNT10:6|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - C 04 OR2 0 4 0 1 |CNT10:6|LPM_ADD_SUB:78|addcore:adder|:69
- 7 - C 04 DFFE 0 4 0 5 |CNT10:6|:8
- 1 - C 04 DFFE 0 5 0 3 |CNT10:6|cq13 (|CNT10:6|:10)
- 2 - C 04 DFFE 0 5 0 3 |CNT10:6|cq12 (|CNT10:6|:11)
- 3 - C 04 DFFE 0 5 0 4 |CNT10:6|cq11 (|CNT10:6|:12)
- 4 - C 04 DFFE 0 3 0 5 |CNT10:6|cq10 (|CNT10:6|:13)
- 5 - C 04 AND2 0 4 0 4 |CNT10:6|:51
- 5 - C 16 AND2 0 2 0 1 |CNT10:7|LPM_ADD_SUB:78|addcore:adder|:55
- 7 - C 16 OR2 0 4 0 1 |CNT10:7|LPM_ADD_SUB:78|addcore:adder|:69
- 5 - C 11 DFFE 0 4 0 4 |CNT10:7|:8
- 8 - C 16 DFFE 0 5 0 3 |CNT10:7|cq13 (|CNT10:7|:10)
- 1 - C 16 DFFE 0 5 0 3 |CNT10:7|cq12 (|CNT10:7|:11)
- 3 - C 16 DFFE 0 5 0 4 |CNT10:7|cq11 (|CNT10:7|:12)
- 4 - C 16 DFFE 0 3 0 5 |CNT10:7|cq10 (|CNT10:7|:13)
- 6 - C 16 AND2 0 4 0 4 |CNT10:7|:51
- 7 - C 11 AND2 0 2 0 1 |CNT10:8|LPM_ADD_SUB:78|addcore:adder|:55
- 8 - C 11 OR2 0 4 0 1 |CNT10:8|LPM_ADD_SUB:78|addcore:adder|:69
- 1 - C 11 DFFE 0 5 0 3 |CNT10:8|cq13 (|CNT10:8|:10)
- 2 - C 11 DFFE 0 5 0 3 |CNT10:8|cq12 (|CNT10:8|:11)
- 4 - C 11 DFFE 0 5 0 4 |CNT10:8|cq11 (|CNT10:8|:12)
- 3 - C 11 DFFE 0 3 0 5 |CNT10:8|cq10 (|CNT10:8|:13)
- 6 - C 11 OR2 ! 0 4 0 3 |CNT10:8|:51
- 7 - C 02 DFFE 1 2 1 0 |FEG24B:2|q23 (|FEG24B:2|:51)
- 6 - C 07 DFFE 1 2 1 0 |FEG24B:2|q22 (|FEG24B:2|:52)
- 5 - C 03 DFFE 1 2 1 0 |FEG24B:2|q21 (|FEG24B:2|:53)
- 4 - C 03 DFFE 1 2 1 0 |FEG24B:2|q20 (|FEG24B:2|:54)
- 2 - C 16 DFFE 1 2 1 0 |FEG24B:2|q19 (|FEG24B:2|:55)
- 1 - C 07 DFFE 1 2 1 0 |FEG24B:2|q18 (|FEG24B:2|:56)
- 8 - C 13 DFFE 1 2 1 0 |FEG24B:2|q17 (|FEG24B:2|:57)
- 8 - C 02 DFFE 1 2 1 0 |FEG24B:2|q16 (|FEG24B:2|:58)
- 5 - C 12 DFFE 1 2 1 0 |FEG24B:2|q15 (|FEG24B:2|:59)
- 8 - C 07 DFFE 1 2 1 0 |FEG24B:2|q14 (|FEG24B:2|:60)
- 1 - C 03 DFFE 1 2 1 0 |FEG24B:2|q13 (|FEG24B:2|:61)
- 2 - C 12 DFFE 1 2 1 0 |FEG24B:2|q12 (|FEG24B:2|:62)
- 4 - C 02 DFFE 1 2 1 0 |FEG24B:2|q11 (|FEG24B:2|:63)
- 5 - C 07 DFFE 1 2 1 0 |FEG24B:2|q10 (|FEG24B:2|:64)
- 6 - C 03 DFFE 1 2 1 0 |FEG24B:2|q9 (|FEG24B:2|:65)
- 7 - C 12 DFFE 1 2 1 0 |FEG24B:2|q8 (|FEG24B:2|:66)
- 1 - C 12 DFFE 1 2 1 0 |FEG24B:2|q7 (|FEG24B:2|:67)
- 3 - C 03 DFFE 1 2 1 0 |FEG24B:2|q6 (|FEG24B:2|:68)
- 4 - C 12 DFFE 1 2 1 0 |FEG24B:2|q5 (|FEG24B:2|:69)
- 8 - C 12 DFFE 1 2 1 0 |FEG24B:2|q4 (|FEG24B:2|:70)
- 5 - C 02 DFFE 1 2 1 0 |FEG24B:2|q3 (|FEG24B:2|:71)
- 8 - C 03 DFFE 1 2 1 0 |FEG24B:2|q2 (|FEG24B:2|:72)
- 1 - C 14 DFFE 1 2 1 0 |FEG24B:2|q1 (|FEG24B:2|:73)
- 3 - C 02 DFFE 1 2 1 0 |FEG24B:2|q0 (|FEG24B:2|:74)
- 2 - C 02 DFFE 1 0 0 31 |TESTCTL:3|div2clk (|TESTCTL:3|:6)
- 6 - C 02 OR2 ! 1 1 0 29 |TESTCTL:3|:39
- 1 - C 02 OR2 1 1 0 24 |TESTCTL:3|:73
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\shumaxianshi9.7\szplj\szpljt.rpt
szpljt
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
B: 0/144( 0%) 6/ 72( 8%) 0/ 72( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 11/144( 7%) 29/ 72( 40%) 0/ 72( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
D: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
E: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
F: 1/144( 0%) 6/ 72( 8%) 0/ 72( 0%) 1/16( 6%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\shumaxianshi9.7\szplj\szpljt.rpt
szpljt
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 25 |TESTCTL:3|:73
DFF 6 |CNT10:1|:8
DFF 6 |CNT10:4|:8
DFF 6 |CNT10:5|:8
DFF 6 |CNT10:6|:8
DFF 5 |CNT10:7|:8
INPUT 5 FSIN
INPUT 3 CLK
Device-Specific Information: d:\shumaxianshi9.7\szplj\szpljt.rpt
szpljt
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 29 |TESTCTL:3|:39
INPUT 24 reset
Device-Specific Information: d:\shumaxianshi9.7\szplj\szpljt.rpt
szpljt
** EQUATIONS **
CLK : INPUT;
FSIN : INPUT;
reset : INPUT;
-- Node name is 'DOUT0'
-- Equation name is 'DOUT0', type is output
DOUT0 = _LC3_C2;
-- Node name is 'DOUT1'
-- Equation name is 'DOUT1', type is output
DOUT1 = _LC1_C14;
-- Node name is 'DOUT2'
-- Equation name is 'DOUT2', type is output
DOUT2 = _LC8_C3;
-- Node name is 'DOUT3'
-- Equation name is 'DOUT3', type is output
DOUT3 = _LC5_C2;
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