📄 lianxiantu.rpt
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Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A25 8/ 8(100%) 4/ 8( 50%) 6/ 8( 75%) 2/2 1/2 2/22( 9%)
A28 8/ 8(100%) 5/ 8( 62%) 1/ 8( 12%) 2/2 2/2 8/22( 36%)
B23 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 9/22( 40%)
B25 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 9/22( 40%)
B28 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 13/22( 59%)
B29 5/ 8( 62%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
B35 4/ 8( 50%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
B36 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 7/22( 31%)
C2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 2/2 9/22( 40%)
C4 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
C6 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 7/22( 31%)
C7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 2/2 12/22( 54%)
C8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 15/22( 68%)
C9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 2/2 13/22( 59%)
C12 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
C13 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
C14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 13/22( 59%)
C18 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 12/22( 54%)
C19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 2/2 8/22( 36%)
C20 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 2/2 12/22( 54%)
C21 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 6/22( 27%)
C22 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
C23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 2/2 10/22( 45%)
C24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 16/22( 72%)
C25 3/ 8( 37%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
C26 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
C27 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 16/22( 72%)
C28 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 13/22( 59%)
C29 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 2/2 1/2 7/22( 31%)
C30 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 2/2 1/2 7/22( 31%)
C31 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 2/2 1/2 9/22( 40%)
C32 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 1/2 8/22( 36%)
C33 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 2/2 11/22( 50%)
C34 5/ 8( 62%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 16/22( 72%)
C35 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 14/22( 63%)
C36 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 12/22( 54%)
D19 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 0/22( 0%)
F19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 1/2 4/22( 18%)
F24 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F25 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
F26 7/ 8( 87%) 6/ 8( 75%) 1/ 8( 12%) 2/2 2/2 10/22( 45%)
F28 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
F33 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 2/2 2/2 14/22( 63%)
F34 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 2/2 6/22( 27%)
F36 5/ 8( 62%) 3/ 8( 37%) 2/ 8( 25%) 1/2 1/2 7/22( 31%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 4/6 ( 66%)
Total I/O pins used: 53/141 ( 37%)
Total logic cells used: 330/1728 ( 19%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.13/4 ( 78%)
Total fan-in: 1035/6912 ( 14%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 45
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 330
Total flipflops required: 146
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 66/1728 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 8 0 0 0 0 0 0 0 0 16/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 0 0 8 5 0 0 0 0 0 4 8 41/0
C: 0 8 0 3 0 8 8 8 1 0 8 8 8 1 0 1 8 7 0 8 8 2 8 8 8 3 8 8 8 8 8 8 8 8 5 8 8 207/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 8 8 7 0 8 0 0 0 0 8 8 0 5 60/0
Total: 0 8 0 3 0 8 8 8 1 0 8 8 8 1 0 1 8 7 0 22 8 2 8 16 16 27 15 8 32 13 8 8 8 16 13 12 21 330/0
Device-Specific Information: d:\chengxu\lianxiantu.rpt
lianxiantu
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - A -- INPUT ^ 0 0 0 3 clk
79 - - - -- INPUT G ^ 0 0 0 0 clk1
183 - - - -- INPUT G ^ 0 0 0 0 FSIN
69 - - - 23 INPUT ^ 0 0 0 3 keydata0
70 - - - 22 INPUT ^ 0 0 0 4 keydata1
71 - - - 21 INPUT ^ 0 0 0 5 keydata2
73 - - - 20 INPUT ^ 0 0 0 5 keydata3
74 - - - 20 INPUT ^ 0 0 0 4 keydata4
75 - - - 19 INPUT ^ 0 0 0 4 keydata5
78 - - - -- INPUT ^ 0 0 0 4 keydata6
80 - - - -- INPUT ^ 0 0 0 3 keydata7
45 - - F -- INPUT ^ 0 0 0 52 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\chengxu\lianxiantu.rpt
lianxiantu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
127 - - D -- OUTPUT 0 1 0 0 DOUT0
128 - - D -- OUTPUT 0 1 0 0 DOUT1
131 - - C -- OUTPUT 0 1 0 0 DOUT2
132 - - C -- OUTPUT 0 1 0 0 DOUT3
133 - - C -- OUTPUT 0 1 0 0 DOUT4
134 - - C -- OUTPUT 0 1 0 0 DOUT5
135 - - C -- OUTPUT 0 1 0 0 DOUT6
136 - - C -- OUTPUT 0 1 0 0 DOUT7
139 - - B -- OUTPUT 0 1 0 0 DOUT8
140 - - B -- OUTPUT 0 1 0 0 DOUT9
141 - - B -- OUTPUT 0 1 0 0 DOUT10
142 - - B -- OUTPUT 0 1 0 0 DOUT11
143 - - B -- OUTPUT 0 1 0 0 DOUT12
144 - - B -- OUTPUT 0 1 0 0 DOUT13
147 - - A -- OUTPUT 0 1 0 0 DOUT14
148 - - A -- OUTPUT 0 1 0 0 DOUT15
120 - - E -- OUTPUT 0 1 0 0 DOUT16
119 - - E -- OUTPUT 0 1 0 0 DOUT17
116 - - F -- OUTPUT 0 1 0 0 DOUT18
115 - - F -- OUTPUT 0 1 0 0 DOUT19
114 - - F -- OUTPUT 0 1 0 0 DOUT20
113 - - F -- OUTPUT 0 1 0 0 DOUT21
112 - - F -- OUTPUT 0 1 0 0 DOUT22
111 - - F -- OUTPUT 0 1 0 0 DOUT23
94 - - - 09 OUTPUT 0 0 0 0 IO_DS1
95 - - - 09 OUTPUT 0 0 0 0 IO_DS2
96 - - - 08 OUTPUT 0 0 0 0 IO_DS3
97 - - - 07 OUTPUT 0 0 0 0 IO_DS4
99 - - - 06 OUTPUT 0 0 0 0 IO_DS5
100 - - - 05 OUTPUT 0 0 0 0 IO_DS6
53 - - - 36 OUTPUT 0 1 0 0 kb0
54 - - - 35 OUTPUT 0 1 0 0 keyout1
55 - - - 34 OUTPUT 0 1 0 0 keyout2
56 - - - 33 OUTPUT 0 1 0 0 keyout3
57 - - - 32 OUTPUT 0 1 0 0 keyout4
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