stopwatch.v

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验,有帮助,

module stopwatch(led_clk, led_rst, led_sel, led_seg, pause);
	input led_clk, led_rst, pause;
	output reg[3:0] led_sel;
	output reg[7:0] led_seg;

	integer countsel, countscan;
	reg [3:0] led_num1, led_num2, led_num3, led_num4;
	reg divclk;
	reg run;

	parameter ZERO = 8'b11111100,ONE = 8'b01100000, TWO = 8'b11011010;
	parameter THREE = 8'b11110010, FOUR =8'b01100110;
	parameter FIVE = 8'b10110110, SIX = 8'b10111110, SEVEN =8'b11100000;
	parameter EIGHT = 8'b11111110, NINE = 8'b11110110, BLANK = 8'b00000000;

	always @(posedge led_clk or negedge led_rst)
	begin
		if (!led_rst)
		begin
			countscan = 0;
			divclk = 0;
		end
		else
		begin
			if (countscan == 99)
			begin
				countscan = 0;
				divclk = ~divclk;
			end
			else
				countscan = countscan + 1;
		end
	end
	
	always @(posedge divclk or negedge led_rst)
	begin
		if (!led_rst)
		begin 
			led_num1 = 0;
			led_num2 = 0;
			led_num3 = 0;
			led_num4 = 0;
			run = 0;
		end
		else if (!pause)
			run = ~run;
		else if(run)
		begin
			if (led_num1 >= 9)
			begin
				led_num1 = 0;
				if (led_num2 >= 9)
				begin
					led_num2 = 0;
					if (led_num3 >= 9)
					begin
						led_num3 = 0;
						if (led_num4 >= 5)
							led_num4 = 0;
						else
							led_num4 = led_num4 + 1;
					end
					else
						led_num3 = led_num3 + 1;	
				end
				else
					led_num2 = led_num2 + 1;
			end
			else
				led_num1 = led_num1 + 1;
		end
		else
		begin
			led_num1 = led_num1;
			led_num2 = led_num2;
			led_num3 = led_num3;
			led_num4 = led_num4;
		end
	end

	always @(posedge led_clk or negedge led_rst)
	begin
		if (!led_rst)
		begin
			countsel = 0;
			led_sel = 4'b0001;						
		end
		else
		begin
				if (countsel == 4)
				begin
					countsel =0;
					if (led_sel == 4'b1000)
						led_sel = 4'b0001;
					else
						led_sel = led_sel << 1;
				end
				countsel = countsel + 1;
		end			
	end

	always @(led_sel)
	begin
		case (led_sel)
			4'b0001 :
			begin
				case (led_num1)
					0 : led_seg = ZERO;
					1 : led_seg = ONE;
					2 : led_seg = TWO;
					3 : led_seg = THREE;
					4 : led_seg = FOUR;
					5 : led_seg = FIVE;
					6 : led_seg = SIX;
					7 : led_seg = SEVEN;
					8 : led_seg = EIGHT;
					9 : led_seg = NINE;
					default : led_seg = BLANK;
				endcase
			end
			4'b0010 :
			begin
				case (led_num2)
					0 : led_seg = ZERO;
					1 : led_seg = ONE;
					2 : led_seg = TWO;
					3 : led_seg = THREE;
					4 : led_seg = FOUR;
					5 : led_seg = FIVE;
					6 : led_seg = SIX;
					7 : led_seg = SEVEN;
					8 : led_seg = EIGHT;
					9 : led_seg = NINE;
					default : led_seg = BLANK;
				endcase
			end
			4'b0100 :
			begin
				case (led_num3)
					0 : led_seg = ZERO+1;
					1 : led_seg = ONE+1;
					2 : led_seg = TWO+1;
					3 : led_seg = THREE+1;
					4 : led_seg = FOUR+1;
					5 : led_seg = FIVE+1;
					6 : led_seg = SIX+1;
					7 : led_seg = SEVEN+1;
					8 : led_seg = EIGHT+1;
					9 : led_seg = NINE+1;
					default : led_seg = BLANK;
				endcase
			end
			4'b1000 :
			begin
				case (led_num4)
					0 : led_seg = ZERO;
					1 : led_seg = ONE;
					2 : led_seg = TWO;
					3 : led_seg = THREE;
					4 : led_seg = FOUR;
					5 : led_seg = FIVE;
					6 : led_seg = SIX;
					7 : led_seg = SEVEN;
					8 : led_seg = EIGHT;
					9 : led_seg = NINE;
					default : led_seg = BLANK;
				endcase
			end
			default
			begin
				led_seg = 'hx;
			end
		endcase
	end

endmodule