displaylcd.ucf

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验,有帮助,

net sysclk loc = p80;	//100khz
net sysrst loc = p57; 
net DI   loc = p206;
net RW  loc = p204;
net EN   loc = p202;
net CSA  loc = p200;
net CSB LOC = P195;
net RST  loc = p193;
net DATA<0> loc = p181;
net DATA<1> loc = p179;
net DATA<2> loc = p176;
net DATA<3> loc = p174;
net DATA<4> loc = p172;
net DATA<5> loc = p167;
net DATA<6> loc = p165;
net DATA<7> loc = p163;
net ctl loc = p102;