dds_all.tan.rpt

这个是相当不错的EDA编程

Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+
; Type                                                  ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                     ; To                                                                                                                                      ; From Clock                             ; To Clock                               ; Failed Paths ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+
; Worst-case tsu                                        ; N/A       ; None                             ; -0.451 ns                        ; altera_internal_jtag~TMSUTAP                                                                                                             ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]                                                                                           ; --                                     ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Worst-case tco                                        ; N/A       ; None                             ; 10.520 ns                        ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_address_reg9 ; FOUT[8]                                                                                                                                 ; CLK                                    ; --                                     ; 0            ;
; Worst-case tpd                                        ; N/A       ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                 ; altera_reserved_tdo                                                                                                                     ; --                                     ; --                                     ; 0            ;
; Worst-case th                                         ; N/A       ; None                             ; 3.646 ns                         ; altera_internal_jtag                                                                                                                     ; SIN_ROM:inst6|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[9]              ; --                                     ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Worst-case Minimum tco                                ; N/A       ; None                             ; 9.241 ns                         ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_address_reg9 ; FOUT[2]                                                                                                                                 ; CLK                                    ; --                                     ; 0            ;
; Worst-case Minimum tpd                                ; N/A       ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                 ; altera_reserved_tdo                                                                                                                     ; --                                     ; --                                     ; 0            ;
; Clock Setup: 'tt:inst1|altpll:altpll_component|_clk0' ; 11.590 ns ; 60.00 MHz ( period = 16.666 ns ) ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1  ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'           ; N/A       ; None                             ; 65.26 MHz ( period = 15.324 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]                                                                                       ; sld_hub:sld_hub_inst|hub_tdo                                                                                                            ; altera_internal_jtag~TCKUTAP           ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Clock Hold: 'tt:inst1|altpll:altpll_component|_clk0'  ; 4.928 ns  ; 60.00 MHz ( period = 16.666 ns ) ; N/A                              ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1  ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                          ;           ;                                  ;                                  ;                                                                                                                                          ;                                                                                                                                         ;                                        ;                                        ; 0            ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;