dds_all.tan.rpt

来自「这个是相当不错的EDA编程」· RPT 代码 · 共 192 行 · 第 1/5 页

; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                         ;
+----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                        ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; tt:inst1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 60.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK      ; 3                     ; 1                   ; -1.833 ns ;              ;
; CLK                                    ;                    ; User Pin   ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP           ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'tt:inst1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+-----------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack     ; Actual fmax (period)             ; From                                                                                                                                    ; To                                                                                                                                      ; From Clock                             ; To Clock                               ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg1 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg1 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_datain_reg0 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a2~porta_memory_reg0 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a5~porta_datain_reg3 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a5~porta_memory_reg3 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a5~porta_datain_reg2 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a5~porta_memory_reg2 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a5~porta_datain_reg1 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a5~porta_memory_reg1 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a5~porta_datain_reg0 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a5~porta_memory_reg0 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_datain_reg3 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_memory_reg3 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_datain_reg2 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_memory_reg2 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_datain_reg1 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_memory_reg1 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
; 11.590 ns ; 197.01 MHz ( period = 5.076 ns ) ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_datain_reg0 ; SIN_ROM:inst5|altsyncram:altsyncram_component|altsyncram_sq71:auto_generated|altsyncram_kol2:altsyncram1|ram_block3a9~porta_memory_reg0 ; tt:inst1|altpll:altpll_component|_clk0 ; tt:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.909 ns                 ; 4.319 ns                ;
+-----------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+