six.hier_info

来自「用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计」· HIER_INFO 代码 · 共 19 行

|six
b[0] <= comb~3
b[1] <= comb~5
b[2] <= comb~7
b[3] <= comb~1
ci => b[3]$latch.LATCH_ENABLE
ci => b[2]$latch.LATCH_ENABLE
ci => b[1]$latch.LATCH_ENABLE
ci => b[0]$latch.LATCH_ENABLE
ci => cou$latch.ACLR
rese => b~11.OUTPUTSELECT
rese => b~10.OUTPUTSELECT
rese => b~9.OUTPUTSELECT
rese => b~8.OUTPUTSELECT
rese => cou$latch.LATCH_ENABLE
cou <= cou$latch.DB_MAX_OUTPUT_PORT_TYPE