prev_cmp_six.tan.qmsg

来自「用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "cin " "Info: Assuming node \"cin\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "reset " "Info: Assuming node \"reset\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 6 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "cin register a\[1\]\$latch register a\[1\]\$latch 227.27 MHz 4.4 ns Internal " "Info: Clock \"cin\" has Internal fmax of 227.27 MHz between source register \"a\[1\]\$latch\" and destination register \"a\[1\]\$latch\" (period= 4.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.068 ns + Longest register register " "Info: + Longest register to register delay is 3.068 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[1\]\$latch 1 REG LC_X12_Y2_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y2_N2; Fanout = 4; REG Node = 'a\[1\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[1]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.187 ns) + CELL(0.442 ns) 1.629 ns Equal0~29 2 COMB LC_X12_Y2_N8 5 " "Info: 2: + IC(1.187 ns) + CELL(0.442 ns) = 1.629 ns; Loc. = LC_X12_Y2_N8; Fanout = 5; COMB Node = 'Equal0~29'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.629 ns" { a[1]$latch Equal0~29 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.795 ns) + CELL(0.114 ns) 2.538 ns a~157 3 COMB LC_X12_Y2_N5 1 " "Info: 3: + IC(0.795 ns) + CELL(0.114 ns) = 2.538 ns; Loc. = LC_X12_Y2_N5; Fanout = 1; COMB Node = 'a~157'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.909 ns" { Equal0~29 a~157 } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.114 ns) 3.068 ns a\[1\]\$latch 4 REG LC_X12_Y2_N2 4 " "Info: 4: + IC(0.416 ns) + CELL(0.114 ns) = 3.068 ns; Loc. = LC_X12_Y2_N2; Fanout = 4; REG Node = 'a\[1\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.530 ns" { a~157 a[1]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.670 ns ( 21.84 % ) " "Info: Total cell delay = 0.670 ns ( 21.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.398 ns ( 78.16 % ) " "Info: Total interconnect delay = 2.398 ns ( 78.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.068 ns" { a[1]$latch Equal0~29 a~157 a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.068 ns" { a[1]$latch {} Equal0~29 {} a~157 {} a[1]$latch {} } { 0.000ns 1.187ns 0.795ns 0.416ns } { 0.000ns 0.442ns 0.114ns 0.114ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cin destination 2.943 ns + Shortest register " "Info: + Shortest clock path from clock \"cin\" to destination register is 2.943 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'cin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.292 ns) 2.943 ns a\[1\]\$latch 2 REG LC_X12_Y2_N2 4 " "Info: 2: + IC(1.182 ns) + CELL(0.292 ns) = 2.943 ns; Loc. = LC_X12_Y2_N2; Fanout = 4; REG Node = 'a\[1\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.474 ns" { cin a[1]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.761 ns ( 59.84 % ) " "Info: Total cell delay = 1.761 ns ( 59.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.182 ns ( 40.16 % ) " "Info: Total interconnect delay = 1.182 ns ( 40.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { cin a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { cin {} cin~out0 {} a[1]$latch {} } { 0.000ns 0.000ns 1.182ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cin source 2.943 ns - Longest register " "Info: - Longest clock path from clock \"cin\" to source register is 2.943 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'cin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.182 ns) + CELL(0.292 ns) 2.943 ns a\[1\]\$latch 2 REG LC_X12_Y2_N2 4 " "Info: 2: + IC(1.182 ns) + CELL(0.292 ns) = 2.943 ns; Loc. = LC_X12_Y2_N2; Fanout = 4; REG Node = 'a\[1\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.474 ns" { cin a[1]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.761 ns ( 59.84 % ) " "Info: Total cell delay = 1.761 ns ( 59.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.182 ns ( 40.16 % ) " "Info: Total interconnect delay = 1.182 ns ( 40.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { cin a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { cin {} cin~out0 {} a[1]$latch {} } { 0.000ns 0.000ns 1.182ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { cin a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { cin {} cin~out0 {} a[1]$latch {} } { 0.000ns 0.000ns 1.182ns } { 0.000ns 1.469ns 0.292ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { cin a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { cin {} cin~out0 {} a[1]$latch {} } { 0.000ns 0.000ns 1.182ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.332 ns + " "Info: + Micro setup delay of destination is 1.332 ns" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.068 ns" { a[1]$latch Equal0~29 a~157 a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.068 ns" { a[1]$latch {} Equal0~29 {} a~157 {} a[1]$latch {} } { 0.000ns 1.187ns 0.795ns 0.416ns } { 0.000ns 0.442ns 0.114ns 0.114ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { cin a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { cin {} cin~out0 {} a[1]$latch {} } { 0.000ns 0.000ns 1.182ns } { 0.000ns 1.469ns 0.292ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.943 ns" { cin a[1]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.943 ns" { cin {} cin~out0 {} a[1]$latch {} } { 0.000ns 0.000ns 1.182ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "a\[3\]\$latch reset cin 7.254 ns register " "Info: tsu for register \"a\[3\]\$latch\" (data pin = \"reset\", clock pin = \"cin\") is 7.254 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.862 ns + Longest pin register " "Info: + Longest pin to register delay is 8.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 CLK PIN_127 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_127; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.045 ns) + CELL(0.292 ns) 7.812 ns a~155 2 COMB LC_X12_Y2_N9 1 " "Info: 2: + IC(6.045 ns) + CELL(0.292 ns) = 7.812 ns; Loc. = LC_X12_Y2_N9; Fanout = 1; COMB Node = 'a~155'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.337 ns" { reset a~155 } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.292 ns) 8.566 ns a~156 3 COMB LC_X12_Y2_N6 1 " "Info: 3: + IC(0.462 ns) + CELL(0.292 ns) = 8.566 ns; Loc. = LC_X12_Y2_N6; Fanout = 1; COMB Node = 'a~156'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.754 ns" { a~155 a~156 } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 8.862 ns a\[3\]\$latch 4 REG LC_X12_Y2_N7 3 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 8.862 ns; Loc. = LC_X12_Y2_N7; Fanout = 3; REG Node = 'a\[3\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { a~156 a[3]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.173 ns ( 24.52 % ) " "Info: Total cell delay = 2.173 ns ( 24.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.689 ns ( 75.48 % ) " "Info: Total interconnect delay = 6.689 ns ( 75.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.862 ns" { reset a~155 a~156 a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.862 ns" { reset {} reset~out0 {} a~155 {} a~156 {} a[3]$latch {} } { 0.000ns 0.000ns 6.045ns 0.462ns 0.182ns } { 0.000ns 1.475ns 0.292ns 0.292ns 0.114ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.333 ns + " "Info: + Micro setup delay of destination is 1.333 ns" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cin destination 2.941 ns - Shortest register " "Info: - Shortest clock path from clock \"cin\" to destination register is 2.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns cin 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'cin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.180 ns) + CELL(0.292 ns) 2.941 ns a\[3\]\$latch 2 REG LC_X12_Y2_N7 3 " "Info: 2: + IC(1.180 ns) + CELL(0.292 ns) = 2.941 ns; Loc. = LC_X12_Y2_N7; Fanout = 3; REG Node = 'a\[3\]\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.472 ns" { cin a[3]$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.761 ns ( 59.88 % ) " "Info: Total cell delay = 1.761 ns ( 59.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.180 ns ( 40.12 % ) " "Info: Total interconnect delay = 1.180 ns ( 40.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.941 ns" { cin a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.941 ns" { cin {} cin~out0 {} a[3]$latch {} } { 0.000ns 0.000ns 1.180ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.862 ns" { reset a~155 a~156 a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.862 ns" { reset {} reset~out0 {} a~155 {} a~156 {} a[3]$latch {} } { 0.000ns 0.000ns 6.045ns 0.462ns 0.182ns } { 0.000ns 1.475ns 0.292ns 0.292ns 0.114ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.941 ns" { cin a[3]$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.941 ns" { cin {} cin~out0 {} a[3]$latch {} } { 0.000ns 0.000ns 1.180ns } { 0.000ns 1.469ns 0.292ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "reset cout cout\$latch 7.443 ns register " "Info: tco from clock \"reset\" to destination pin \"cout\" through register \"cout\$latch\" is 7.443 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset source 3.907 ns + Longest register " "Info: + Longest clock path from clock \"reset\" to source register is 3.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 CLK PIN_127 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_127; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.140 ns) + CELL(0.292 ns) 3.907 ns cout\$latch 2 REG LC_X12_Y4_N3 1 " "Info: 2: + IC(2.140 ns) + CELL(0.292 ns) = 3.907 ns; Loc. = LC_X12_Y4_N3; Fanout = 1; REG Node = 'cout\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.432 ns" { reset cout$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.767 ns ( 45.23 % ) " "Info: Total cell delay = 1.767 ns ( 45.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.140 ns ( 54.77 % ) " "Info: Total interconnect delay = 2.140 ns ( 54.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.907 ns" { reset cout$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.907 ns" { reset {} reset~out0 {} cout$latch {} } { 0.000ns 0.000ns 2.140ns } { 0.000ns 1.475ns 0.292ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.536 ns + Longest register pin " "Info: + Longest register to pin delay is 3.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cout\$latch 1 REG LC_X12_Y4_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y4_N3; Fanout = 1; REG Node = 'cout\$latch'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cout$latch } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 11 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.428 ns) + CELL(2.108 ns) 3.536 ns cout 2 PIN PIN_53 0 " "Info: 2: + IC(1.428 ns) + CELL(2.108 ns) = 3.536 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'cout'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.536 ns" { cout$latch cout } "NODE_NAME" } } { "six.vhd" "" { Text "D:/EDA/030501713/time/six.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 59.62 % ) " "Info: Total cell delay = 2.108 ns ( 59.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.428 ns ( 40.38 % ) " "Info: Total interconnect delay = 1.428 ns ( 40.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.536 ns" { cout$latch cout } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.536 ns" { cout$latch {} cout {} } { 0.000ns 1.428ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.907 ns" { reset cout$latch } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.907 ns" { reset {} reset~out0 {} cout$latch {} } { 0.000ns 0.000ns 2.140ns } { 0.000ns 1.475ns 0.292ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.536 ns" { cout$latch cout } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.536 ns" { cout$latch {} cout {} } { 0.000ns 1.428ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}