decoder.hier_info

用ＶＨＤＬ来模拟实现钟最终实现数字电子钟的设计

|decoder
d[0] => Mux6.IN19
d[0] => Mux5.IN19
d[0] => Mux4.IN19
d[0] => Mux3.IN19
d[0] => Mux2.IN19
d[0] => Mux1.IN19
d[0] => Mux0.IN19
d[1] => Mux6.IN18
d[1] => Mux5.IN18
d[1] => Mux4.IN18
d[1] => Mux3.IN18
d[1] => Mux2.IN18
d[1] => Mux1.IN18
d[1] => Mux0.IN18
d[2] => Mux6.IN17
d[2] => Mux5.IN17
d[2] => Mux4.IN17
d[2] => Mux3.IN17
d[2] => Mux2.IN17
d[2] => Mux1.IN17
d[2] => Mux0.IN17
d[3] => Mux6.IN16
d[3] => Mux5.IN16
d[3] => Mux4.IN16
d[3] => Mux3.IN16
d[3] => Mux2.IN16
d[3] => Mux1.IN16
d[3] => Mux0.IN16
x[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
x[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
x[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
x[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
x[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
x[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
x[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE