fourbitadder.tan.qmsg

用VHDL语言采用串行方法实现用1位全加器实现4位全加器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 19 09:18:22 2008 " "Info: Processing started: Sat Apr 19 09:18:22 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off fourbitadder -c fourbitadder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fourbitadder -c fourbitadder --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "x\[1\] dcount 12.061 ns Longest " "Info: Longest tpd from source pin \"x\[1\]\" to destination pin \"dcount\" is 12.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns x\[1\] 1 PIN PIN_110 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_110; Fanout = 2; PIN Node = 'x\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { x[1] } "NODE_NAME" } } { "fourbitadder.vhd" "" { Text "G:/f_adder/fourbitadder.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.058 ns) + CELL(0.590 ns) 7.123 ns onebitadder:U1\|count~7 2 COMB LC_X26_Y11_N5 2 " "Info: 2: + IC(5.058 ns) + CELL(0.590 ns) = 7.123 ns; Loc. = LC_X26_Y11_N5; Fanout = 2; COMB Node = 'onebitadder:U1\|count~7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.648 ns" { x[1] onebitadder:U1|count~7 } "NODE_NAME" } } { "onebitadder.vhd" "" { Text "G:/f_adder/onebitadder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.114 ns) 7.666 ns onebitadder:U2\|count~74 3 COMB LC_X26_Y11_N7 2 " "Info: 3: + IC(0.429 ns) + CELL(0.114 ns) = 7.666 ns; Loc. = LC_X26_Y11_N7; Fanout = 2; COMB Node = 'onebitadder:U2\|count~74'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.543 ns" { onebitadder:U1|count~7 onebitadder:U2|count~74 } "NODE_NAME" } } { "onebitadder.vhd" "" { Text "G:/f_adder/onebitadder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.449 ns) + CELL(0.292 ns) 8.407 ns onebitadder:U3\|count~131 4 COMB LC_X26_Y11_N9 1 " "Info: 4: + IC(0.449 ns) + CELL(0.292 ns) = 8.407 ns; Loc. = LC_X26_Y11_N9; Fanout = 1; COMB Node = 'onebitadder:U3\|count~131'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.741 ns" { onebitadder:U2|count~74 onebitadder:U3|count~131 } "NODE_NAME" } } { "onebitadder.vhd" "" { Text "G:/f_adder/onebitadder.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.530 ns) + CELL(2.124 ns) 12.061 ns dcount 5 PIN PIN_100 0 " "Info: 5: + IC(1.530 ns) + CELL(2.124 ns) = 12.061 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'dcount'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.654 ns" { onebitadder:U3|count~131 dcount } "NODE_NAME" } } { "fourbitadder.vhd" "" { Text "G:/f_adder/fourbitadder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.595 ns ( 38.10 % ) " "Info: Total cell delay = 4.595 ns ( 38.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.466 ns ( 61.90 % ) " "Info: Total interconnect delay = 7.466 ns ( 61.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.061 ns" { x[1] onebitadder:U1|count~7 onebitadder:U2|count~74 onebitadder:U3|count~131 dcount } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.061 ns" { x[1] x[1]~out0 onebitadder:U1|count~7 onebitadder:U2|count~74 onebitadder:U3|count~131 dcount } { 0.000ns 0.000ns 5.058ns 0.429ns 0.449ns 1.530ns } { 0.000ns 1.475ns 0.590ns 0.114ns 0.292ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 19 09:18:22 2008 " "Info: Processing ended: Sat Apr 19 09:18:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}