div_ctl.v

来自「基于srt-2算法」· Verilog 代码 · 共 59 行

module div_ctl(clk,reset,start,wrg,fsh,rdy,run,err,ok);
    input clk,reset,start,wrg,fsh;
    output rdy,run,err,ok;
    wire clk,reset,start;
    reg rdy,run,err,ok;
    
    parameter IDLE = 3'B001;
    parameter RUN = 3'b010;
    parameter FINISH = 3'b100;
    
    reg [2:0] current_state,next_state;
    
    always @ (posedge clk or negedge reset)
    begin
        if(!reset) current_state <= IDLE;
        else current_state <= next_state;
    end
    
    always @ (current_state or start or wrg or fsh)
    begin
        case(current_state)
            IDLE:begin
                rdy <= 0;
                run <= 0;
                ok <= 0;
                err <= 0;
                if(start)
                begin
                    rdy <= 1;
                    err <= 0;
                    ok <= 0;
                    run <= 0;
                    next_state <= RUN;
                end
                else next_state <= IDLE;
            end
            RUN:begin
                run <= 1;
                rdy <= 0;
                if(wrg)
                begin
                    err <= 1;
                    next_state <= FINISH;
                end
                else if(fsh) next_state <= FINISH;
                else next_state <= RUN;
            end
            FINISH:begin
                run <= 0;
                if(!reset) next_state <= IDLE;
                else begin
                    ok <= 1;
                    next_state <= FINISH;
                end
            end
            default:next_state <= IDLE;
        endcase
    end
endmodule