divider.v

来自「基于srt-2算法」· Verilog 代码 · 共 31 行

module div2(clk,reset,start,dividend,divisor,quo,rem,err,ok);
    parameter n=32;
    parameter m=16;
    
    input clk,reset,start;
    input [n-1:0] dividend,divisor;
    output [n+m-1:0] quo;
    output [n-1:0] rem;
    output err,ok;
    wire clk,reset,start;
    wire [n-1:0] dividend,divisor;
    wire [n+m-1:0] quo;
    wire  [n-1:0] rem;
    wire err,ok;
    
    wire rdy,fsh,run,wrg;
    
    div_ctl UCTL(clk,reset,start,wrg,fsh,rdy,run,err,ok);
    
    div_datapath #(n,m) UDATAPATH(clk,reset,rdy,dividend,
                  divisor,run,wrg,fsh,quo,rem);
endmodule