📄 can_parts.vhd
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--// can_btl.v ////
--// ////
--// ////
--// This file is part of the CAN Protocol Controller ////
--// http://www.opencores.org/projects/can/ ////
--// ////
--// ////
--// Author(s): ////
--// Igor Mohor ////
--// igorm@opencores.org ////
--// ////
--// ////
--// All additional information is available in the README.txt ////
--// file. ////
--// ////
--////////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2002, 2003, 2004 Authors ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer. ////
--// ////
--// This source file is free software; you can redistribute it ////
--// and/or modify it under the terms of the GNU Lesser General ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any ////
--// later version. ////
--// ////
--// This source is distributed in the hope that it will be ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
--// PURPOSE. See the GNU Lesser General Public License for more ////
--// details. ////
--// ////
--// You should have received a copy of the GNU Lesser General ////
--// Public License along with this source; if not, download it ////
--// from http://www.opencores.org/lgpl.shtml ////
--// ////
--// The CAN protocol is developed by Robert Bosch GmbH and ////
--// protected by patents. Anybody who wants to implement this ////
--// CAN IP core on silicon has to obtain a CAN protocol license ////
--// from Bosch. ////
--// ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_btl.v,v $
-- Revision 1.30 2004/10/27 18:51:37 igorm
-- Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
--
-- Revision 1.29 2004/05/12 15:58:41 igorm
-- Core improved to pass all tests with the Bosch VHDL Reference system.
--
-- Revision 1.28 2004/02/08 14:25:26 mohor
-- Header changed.
--
-- Revision 1.27 2003/09/30 00:55:13 mohor
-- Error counters fixed to be compatible with Bosch VHDL reference model.
-- Small synchronization changes.
--
-- Revision 1.26 2003/09/25 18:55:49 mohor
-- Synchronization changed, error counters fixed.
--
-- Revision 1.25 2003/07/16 13:40:35 mohor
-- Fixed according to the linter.
--
-- Revision 1.24 2003/07/10 15:32:28 mohor
-- Unused signal removed.
--
-- Revision 1.23 2003/07/10 01:59:04 tadejm
-- Synchronization fixed. In some strange cases it didn't work according to
-- the VHDL reference model.
--
-- Revision 1.22 2003/07/07 11:21:37 mohor
-- Little fixes (to fix warnings).
--
-- Revision 1.21 2003/07/03 09:32:20 mohor
-- Synchronization changed.
--
-- Revision 1.20 2003/06/20 14:51:11 mohor
-- Previous change removed. When resynchronization occurs we go to seg1
-- stage. sync stage does not cause another start of seg1 stage.
--
-- Revision 1.19 2003/06/20 14:28:20 mohor
-- When hard_sync or resync occure we need to go to seg1 segment. Going to
-- sync segment is in that case blocked.
--
-- Revision 1.18 2003/06/17 15:53:33 mohor
-- clk_cnt reduced from [8:0] to [6:0].
--
-- Revision 1.17 2003/06/17 14:32:17 mohor
-- Removed few signals.
--
-- Revision 1.16 2003/06/16 13:57:58 mohor
-- tx_point generated one clk earlier. rx_i registered. Data corrected when
-- using extended mode.
--
-- Revision 1.15 2003/06/13 15:02:24 mohor
-- Synchronization is also needed when transmitting a message.
--
-- Revision 1.14 2003/06/13 14:55:11 mohor
-- Counters width changed.
--
-- Revision 1.13 2003/06/11 14:21:35 mohor
-- When switching to tx, sync stage is overjumped.
--
-- Revision 1.12 2003/02/14 20:17:01 mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.11 2003/02/09 18:40:29 mohor
-- Overload fixed. Hard synchronization also enabled at the last bit of
-- interframe.
--
-- Revision 1.10 2003/02/09 02:24:33 mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.9 2003/01/31 01:13:38 mohor
-- backup.
--
-- Revision 1.8 2003/01/10 17:51:34 mohor
-- Temporary version (backup).
--
-- Revision 1.7 2003/01/08 02:10:53 mohor
-- Acceptance filter added.
--
-- Revision 1.6 2002/12/28 04:13:23 mohor
-- Backup version.
--
-- Revision 1.5 2002/12/27 00:12:52 mohor
-- Header changed, testbench improved to send a frame (crc still missing).
--
-- Revision 1.4 2002/12/26 01:33:05 mohor
-- Tripple sampling supported.
--
-- Revision 1.3 2002/12/25 23:44:16 mohor
-- Commented lines removed.
--
-- Revision 1.2 2002/12/25 14:17:00 mohor
-- Synchronization working.
--
-- Revision 1.1.1.1 2002/12/20 16:39:21 mohor
-- Initial
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY can_vhdl_btl IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
rx : IN std_logic;
tx : IN std_logic;
-- Bus Timing 0 register
baud_r_presc : IN std_logic_vector(5 DOWNTO 0);
sync_jump_width : IN std_logic_vector(1 DOWNTO 0);
-- Bus Timing 1 register
time_segment1 : IN std_logic_vector(3 DOWNTO 0);
time_segment2 : IN std_logic_vector(2 DOWNTO 0);
triple_sampling : IN std_logic;
-- Output signals from this module
sample_point : OUT std_logic;
sampled_bit : OUT std_logic;
sampled_bit_q : OUT std_logic;
tx_point : OUT std_logic;
hard_sync : OUT std_logic;
-- Output from can_bsp module
rx_idle : IN std_logic;
rx_inter : IN std_logic;
transmitting : IN std_logic;
transmitter : IN std_logic;
go_rx_inter : IN std_logic;
tx_next : IN std_logic;
go_overload_frame : IN std_logic;
go_error_frame : IN std_logic;
go_tx : IN std_logic;
send_ack : IN std_logic;
node_error_passive : IN std_logic);
END ENTITY can_vhdl_btl;
ARCHITECTURE RTL OF can_vhdl_btl IS
function conv_std_logic(b : boolean) return std_ulogic is
begin
if b then return('1'); else return('0'); end if;
end;
TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);
SIGNAL clk_cnt : std_logic_vector(6 DOWNTO 0);
SIGNAL clk_en : std_logic;
SIGNAL clk_en_q : std_logic;
SIGNAL sync_blocked : std_logic;
SIGNAL hard_sync_blocked : std_logic;
SIGNAL quant_cnt : std_logic_vector(4 DOWNTO 0);
SIGNAL delay : std_logic_vector(3 DOWNTO 0);
SIGNAL sync : std_logic;
SIGNAL seg1 : std_logic;
SIGNAL seg2 : std_logic;
SIGNAL resync_latched : std_logic;
SIGNAL sample : std_logic_vector(1 DOWNTO 0);
SIGNAL tx_next_sp : std_logic;
SIGNAL go_sync : std_logic;
SIGNAL go_seg1 : std_logic;
SIGNAL go_seg2 : std_logic;
SIGNAL preset_cnt : std_logic_vector(7 DOWNTO 0);
SIGNAL sync_window : std_logic;
SIGNAL resync : std_logic;
-- when transmitting 0 with positive error delay is set to 0
SIGNAL temp_xhdl6 : std_logic_vector(4 DOWNTO 0);
SIGNAL sample_point_xhdl1 : std_logic;
SIGNAL sampled_bit_xhdl2 : std_logic;
SIGNAL sampled_bit_q_xhdl3 : std_logic;
SIGNAL tx_point_xhdl4 : std_logic;
SIGNAL hard_sync_xhdl5 : std_logic;
BEGIN
sample_point <= sample_point_xhdl1;
sampled_bit <= sampled_bit_xhdl2;
sampled_bit_q <= sampled_bit_q_xhdl3;
tx_point <= tx_point_xhdl4;
hard_sync <= hard_sync_xhdl5;
preset_cnt <= (('0' & baud_r_presc) + 1) & "0" ;
hard_sync_xhdl5 <= (((rx_idle OR rx_inter) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT hard_sync_blocked) ;
resync <= ((((NOT rx_idle) AND (NOT rx_inter)) AND (NOT rx)) AND sampled_bit_xhdl2) AND (NOT sync_blocked) ;
-- Generating general enable signal that defines baud rate.
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_cnt <= "0000000";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) >= (preset_cnt - "00000001")) THEN
clk_cnt <= "0000000" ;
ELSE
clk_cnt <= clk_cnt + "0000001" ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (('0' & clk_cnt) = (preset_cnt - "00000001")) THEN
clk_en <= '1' ;
ELSE
clk_en <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
clk_en_q <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
clk_en_q <= clk_en ;
END IF;
END PROCESS;
-- Changing states
go_sync <= (((clk_en_q AND seg2) AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) AND (NOT hard_sync_xhdl5)) AND (NOT resync) ;
go_seg1 <= clk_en_q AND (sync OR hard_sync_xhdl5 OR ((resync AND seg2) AND sync_window) OR (resync_latched AND sync_window)) ;
go_seg2 <= clk_en_q AND ((seg1 AND (NOT hard_sync_xhdl5)) AND CONV_STD_LOGIC(quant_cnt = ( '0' & (time_segment1 + delay)))) ;
PROCESS (clk, rst)
BEGIN
IF (rst = '1') THEN
tx_point_xhdl4 <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
tx_point_xhdl4 <= (NOT tx_point_xhdl4 AND seg2) AND ((clk_en AND CONV_STD_LOGIC(quant_cnt(2 DOWNTO 0) = time_segment2)) OR ((clk_en OR clk_en_q) AND (resync OR hard_sync_xhdl5))) ; -- When transmitter we should transmit as soon as possible.
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