controlunit.fit.qmsg

CPU设计中的controlunit源码

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.098 ns memory register " "Info: Estimated most critical path is memory to register delay of 8.098 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|ram_block1a5~porta_address_reg0 1 MEM M512_X20_Y35 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X20_Y35; Fanout = 1; MEM Node = 'lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|ram_block1a5~porta_address_reg0'" {  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a5~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_vcp.tdf" "" { Text "E:/workspace/project/db/altsyncram_vcp.tdf" 138 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.066 ns) 3.066 ns lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|q_a\[5\] 2 MEM M512_X20_Y35 2 " "Info: 2: + IC(0.000 ns) + CELL(3.066 ns) = 3.066 ns; Loc. = M512_X20_Y35; Fanout = 2; MEM Node = 'lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|q_a\[5\]'" {  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.066 ns" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a5~porta_address_reg0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] } "NODE_NAME" } "" } } { "db/altsyncram_vcp.tdf" "" { Text "E:/workspace/project/db/altsyncram_vcp.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.213 ns) 4.512 ns CAR\[1\]~2003 3 COMB LAB_X25_Y34 4 " "Info: 3: + IC(1.233 ns) + CELL(0.213 ns) = 4.512 ns; Loc. = LAB_X25_Y34; Fanout = 4; COMB Node = 'CAR\[1\]~2003'" {  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "1.446 ns" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] CAR[1]~2003 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.694 ns) + CELL(0.332 ns) 5.538 ns CAR\[1\]~2011 4 COMB LAB_X23_Y34 2 " "Info: 4: + IC(0.694 ns) + CELL(0.332 ns) = 5.538 ns; Loc. = LAB_X23_Y34; Fanout = 2; COMB Node = 'CAR\[1\]~2011'" {  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "1.026 ns" { CAR[1]~2003 CAR[1]~2011 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 6.052 ns CAR\[5\]~2024 5 COMB LAB_X23_Y34 2 " "Info: 5: + IC(0.427 ns) + CELL(0.087 ns) = 6.052 ns; Loc. = LAB_X23_Y34; Fanout = 2; COMB Node = 'CAR\[5\]~2024'" {  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "0.514 ns" { CAR[1]~2011 CAR[5]~2024 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.726 ns) 8.098 ns CAR\[7\] 6 REG LAB_X25_Y35 9 " "Info: 6: + IC(1.320 ns) + CELL(0.726 ns) = 8.098 ns; Loc. = LAB_X25_Y35; Fanout = 9; REG Node = 'CAR\[7\]'" {  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.046 ns" { CAR[5]~2024 CAR[7] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.424 ns ( 54.63 % ) " "Info: Total cell delay = 4.424 ns ( 54.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.674 ns ( 45.37 % ) " "Info: Total interconnect delay = 3.674 ns ( 45.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "8.098 ns" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a5~porta_address_reg0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] CAR[1]~2003 CAR[1]~2011 CAR[5]~2024 CAR[7] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 18 08:50:53 2008 " "Info: Processing ended: Fri Apr 18 08:50:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}