controlunit.map.qmsg

CPU设计中的controlunit源码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram LPM_ROM:U5\|altrom:srom\|altsyncram:rom_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"LPM_ROM:U5\|altrom:srom\|altsyncram:rom_block\"" {  } { { "altrom.tdf" "rom_block" { Text "d:/program files/quartus51/libraries/megafunctions/altrom.tdf" 88 7 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vcp.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vcp.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vcp " "Info: Found entity 1: altsyncram_vcp" {  } { { "db/altsyncram_vcp.tdf" "" { Text "E:/workspace/project/db/altsyncram_vcp.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_vcp LPM_ROM:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated " "Info: Elaborating entity \"altsyncram_vcp\" for hierarchy \"LPM_ROM:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "we High " "Info: Power-up level of register \"we\" is not specified -- using power-up level of High to minimize register" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 38 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "we data_in VCC " "Warning: Reduced register \"we\" with stuck data_in port to stuck value VCC" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 38 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_rom:U5\|otri\[7\] " "Warning: Converting TRI node \"lpm_rom:U5\|otri\[7\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_rom:U5\|otri\[6\] " "Warning: Converting TRI node \"lpm_rom:U5\|otri\[6\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_rom:U5\|otri\[5\] " "Warning: Converting TRI node \"lpm_rom:U5\|otri\[5\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_rom:U5\|otri\[4\] " "Warning: Converting TRI node \"lpm_rom:U5\|otri\[4\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_rom:U5\|otri\[3\] " "Warning: Converting TRI node \"lpm_rom:U5\|otri\[3\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_rom:U5\|otri\[2\] " "Warning: Converting TRI node \"lpm_rom:U5\|otri\[2\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_rom:U5\|otri\[1\] " "Warning: Converting TRI node \"lpm_rom:U5\|otri\[1\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "lpm_rom:U5\|otri\[0\] " "Warning: Converting TRI node \"lpm_rom:U5\|otri\[0\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "d:/program files/quartus51/libraries/megafunctions/LPM_ROM.tdf" 65 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "temp\[5\] temp\[7\] " "Info: Duplicate register \"temp\[5\]\" merged to single register \"temp\[7\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp\[6\] temp\[7\] " "Info: Duplicate register \"temp\[6\]\" merged to single register \"temp\[7\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp\[4\] temp\[7\] " "Info: Duplicate register \"temp\[4\]\" merged to single register \"temp\[7\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp\[0\] temp\[3\] " "Info: Duplicate register \"temp\[0\]\" merged to single register \"temp\[3\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp\[2\] temp\[3\] " "Info: Duplicate register \"temp\[2\]\" merged to single register \"temp\[3\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "temp\[1\] temp\[3\] " "Info: Duplicate register \"temp\[1\]\" merged to single register \"temp\[3\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "temp\[7\] data_in GND " "Warning: Reduced register \"temp\[7\]\" with stuck data_in port to stuck value GND" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "temp\[3\] High " "Info: Power-up level of register \"temp\[3\]\" is not specified -- using power-up level of High to minimize register" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "temp\[3\] data_in VCC " "Warning: Reduced register \"temp\[3\]\" with stuck data_in port to stuck value VCC" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "6 " "Warning: Design contains 6 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "flag\[0\] " "Warning: No output dependent on input pin \"flag\[0\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 26 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "flag\[1\] " "Warning: No output dependent on input pin \"flag\[1\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 26 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "flag\[2\] " "Warning: No output dependent on input pin \"flag\[2\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 26 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "flag\[3\] " "Warning: No output dependent on input pin \"flag\[3\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 26 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "flag\[5\] " "Warning: No output dependent on input pin \"flag\[5\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 26 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "flag\[6\] " "Warning: No output dependent on input pin \"flag\[6\]\"" {  } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 26 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "116 " "Info: Implemented 116 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "83 " "Info: Implemented 83 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 18 08:50:40 2008 " "Info: Processing ended: Fri Apr 18 08:50:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}