controlunit.hier_info

CPU设计中的controlunit源码

|controlunit
clk => CAR[7].CLK
clk => CAR[6].CLK
clk => CAR[5].CLK
clk => CAR[4].CLK
clk => CAR[3].CLK
clk => CAR[2].CLK
clk => CAR[1].CLK
clk => CAR[0].CLK
clk => temp[7].CLK
clk => temp[6].CLK
clk => temp[5].CLK
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
clk => control_signal[7]~reg0.CLK
clk => control_signal[6]~reg0.CLK
clk => control_signal[5]~reg0.CLK
clk => control_signal[4]~reg0.CLK
clk => control_signal[3]~reg0.CLK
clk => control_signal[2]~reg0.CLK
clk => control_signal[1]~reg0.CLK
clk => control_signal[0]~reg0.CLK
clk => LPM_ROM:U5.INCLOCK
clk => we.CLK
flag[0] => ~NO_FANOUT~
flag[1] => ~NO_FANOUT~
flag[2] => ~NO_FANOUT~
flag[3] => ~NO_FANOUT~
flag[4] => CAR~0.DATAB
flag[5] => ~NO_FANOUT~
flag[6] => ~NO_FANOUT~
flag[7] => Mux~15.IN255
flag[7] => CAR~0.OUTPUTSELECT
flag[7] => temp~0.OUTPUTSELECT
flag[7] => temp~1.OUTPUTSELECT
flag[7] => temp~2.OUTPUTSELECT
flag[7] => temp~3.OUTPUTSELECT
flag[7] => temp~4.OUTPUTSELECT
flag[7] => temp~5.OUTPUTSELECT
flag[7] => temp~6.OUTPUTSELECT
flag[7] => temp~7.OUTPUTSELECT
flag[7] => CAR~1.OUTPUTSELECT
flag[7] => CAR~2.OUTPUTSELECT
flag[7] => CAR~3.OUTPUTSELECT
flag[7] => CAR~4.OUTPUTSELECT
flag[7] => CAR~5.OUTPUTSELECT
flag[7] => CAR~6.OUTPUTSELECT
flag[7] => CAR~7.OUTPUTSELECT
flag[7] => CAR~8.OUTPUTSELECT
flag[7] => Mux~13.IN2
IR[0] => Mux~0.IN263
IR[0] => Mux~1.IN263
IR[0] => Mux~2.IN263
IR[0] => Mux~3.IN263
IR[1] => Mux~0.IN262
IR[1] => Mux~1.IN262
IR[1] => Mux~2.IN262
IR[1] => Mux~3.IN262
IR[2] => Mux~0.IN261
IR[2] => Mux~1.IN261
IR[2] => Mux~2.IN261
IR[2] => Mux~3.IN261
IR[3] => Mux~0.IN260
IR[3] => Mux~1.IN260
IR[3] => Mux~2.IN260
IR[3] => Mux~3.IN260
IR[4] => Mux~0.IN259
IR[4] => Mux~1.IN259
IR[4] => Mux~2.IN259
IR[4] => Mux~3.IN259
IR[5] => Mux~0.IN258
IR[5] => Mux~1.IN258
IR[5] => Mux~2.IN258
IR[5] => Mux~3.IN258
IR[6] => Mux~0.IN257
IR[6] => Mux~1.IN257
IR[6] => Mux~2.IN257
IR[6] => Mux~3.IN257
IR[7] => Mux~0.IN256
IR[7] => Mux~1.IN256
IR[7] => Mux~2.IN256
IR[7] => Mux~3.IN256
control_signal[0] <= control_signal[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
control_signal[1] <= control_signal[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
control_signal[2] <= control_signal[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
control_signal[3] <= control_signal[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
control_signal[4] <= control_signal[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
control_signal[5] <= control_signal[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
control_signal[6] <= control_signal[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
control_signal[7] <= control_signal[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|controlunit|LPM_ROM:U5
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
inclock => altrom:srom.clocki
outclock => ~NO_FANOUT~
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE


|controlunit|LPM_ROM:U5|altrom:srom
address[0] => altsyncram:rom_block.address_a[0]
address[1] => altsyncram:rom_block.address_a[1]
address[2] => altsyncram:rom_block.address_a[2]
address[3] => altsyncram:rom_block.address_a[3]
address[4] => altsyncram:rom_block.address_a[4]
address[5] => altsyncram:rom_block.address_a[5]
address[6] => altsyncram:rom_block.address_a[6]
address[7] => altsyncram:rom_block.address_a[7]
clocki => altsyncram:rom_block.clock0
clocko => ~NO_FANOUT~
q[0] <= altsyncram:rom_block.q_a[0]
q[1] <= altsyncram:rom_block.q_a[1]
q[2] <= altsyncram:rom_block.q_a[2]
q[3] <= altsyncram:rom_block.q_a[3]
q[4] <= altsyncram:rom_block.q_a[4]
q[5] <= altsyncram:rom_block.q_a[5]
q[6] <= altsyncram:rom_block.q_a[6]
q[7] <= altsyncram:rom_block.q_a[7]


|controlunit|LPM_ROM:U5|altrom:srom|altsyncram:rom_block
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_vcp:auto_generated.address_a[0]
address_a[1] => altsyncram_vcp:auto_generated.address_a[1]
address_a[2] => altsyncram_vcp:auto_generated.address_a[2]
address_a[3] => altsyncram_vcp:auto_generated.address_a[3]
address_a[4] => altsyncram_vcp:auto_generated.address_a[4]
address_a[5] => altsyncram_vcp:auto_generated.address_a[5]
address_a[6] => altsyncram_vcp:auto_generated.address_a[6]
address_a[7] => altsyncram_vcp:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_vcp:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_vcp:auto_generated.q_a[0]
q_a[1] <= altsyncram_vcp:auto_generated.q_a[1]
q_a[2] <= altsyncram_vcp:auto_generated.q_a[2]
q_a[3] <= altsyncram_vcp:auto_generated.q_a[3]
q_a[4] <= altsyncram_vcp:auto_generated.q_a[4]
q_a[5] <= altsyncram_vcp:auto_generated.q_a[5]
q_a[6] <= altsyncram_vcp:auto_generated.q_a[6]
q_a[7] <= altsyncram_vcp:auto_generated.q_a[7]
q_b[0] <= <GND>


|controlunit|LPM_ROM:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT