📄 controlunit.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|ram_block1a1~porta_address_reg0 register CAR\[5\] 112.15 MHz 8.917 ns Internal " "Info: Clock \"clk\" has Internal fmax of 112.15 MHz between source memory \"lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|ram_block1a1~porta_address_reg0\" and destination register \"CAR\[5\]\" (period= 8.917 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.586 ns + Longest memory register " "Info: + Longest memory to register delay is 8.586 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|ram_block1a1~porta_address_reg0 1 MEM M512_X20_Y35 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X20_Y35; Fanout = 2; MEM Node = 'lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|ram_block1a1~porta_address_reg0'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_vcp.tdf" "" { Text "E:/workspace/project/db/altsyncram_vcp.tdf" 62 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.066 ns) 3.066 ns lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|q_a\[5\] 2 MEM M512_X20_Y35 2 " "Info: 2: + IC(0.000 ns) + CELL(3.066 ns) = 3.066 ns; Loc. = M512_X20_Y35; Fanout = 2; MEM Node = 'lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|q_a\[5\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.066 ns" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] } "NODE_NAME" } "" } } { "db/altsyncram_vcp.tdf" "" { Text "E:/workspace/project/db/altsyncram_vcp.tdf" 40 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.276 ns) + CELL(0.459 ns) 4.801 ns CAR\[1\]~2003 3 COMB LC_X25_Y34_N5 4 " "Info: 3: + IC(1.276 ns) + CELL(0.459 ns) = 4.801 ns; Loc. = LC_X25_Y34_N5; Fanout = 4; COMB Node = 'CAR\[1\]~2003'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "1.735 ns" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] CAR[1]~2003 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.087 ns) 5.468 ns CAR\[1\]~2008 4 COMB LC_X25_Y34_N7 4 " "Info: 4: + IC(0.580 ns) + CELL(0.087 ns) = 5.468 ns; Loc. = LC_X25_Y34_N7; Fanout = 4; COMB Node = 'CAR\[1\]~2008'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "0.667 ns" { CAR[1]~2003 CAR[1]~2008 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.459 ns) 6.302 ns Mux~10094 5 COMB LC_X25_Y34_N4 3 " "Info: 5: + IC(0.375 ns) + CELL(0.459 ns) = 6.302 ns; Loc. = LC_X25_Y34_N4; Fanout = 3; COMB Node = 'Mux~10094'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "0.834 ns" { CAR[1]~2008 Mux~10094 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.459 ns) 7.649 ns Mux~10102 6 COMB LC_X22_Y34_N8 1 " "Info: 6: + IC(0.888 ns) + CELL(0.459 ns) = 7.649 ns; Loc. = LC_X22_Y34_N8; Fanout = 1; COMB Node = 'Mux~10102'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "1.347 ns" { Mux~10094 Mux~10102 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.583 ns) 8.586 ns CAR\[5\] 7 REG LC_X22_Y34_N9 7 " "Info: 7: + IC(0.354 ns) + CELL(0.583 ns) = 8.586 ns; Loc. = LC_X22_Y34_N9; Fanout = 7; REG Node = 'CAR\[5\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "0.937 ns" { Mux~10102 CAR[5] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.113 ns ( 59.55 % ) " "Info: Total cell delay = 5.113 ns ( 59.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.473 ns ( 40.45 % ) " "Info: Total interconnect delay = 3.473 ns ( 40.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "8.586 ns" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] CAR[1]~2003 CAR[1]~2008 Mux~10094 Mux~10102 CAR[5] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "8.586 ns" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] CAR[1]~2003 CAR[1]~2008 Mux~10094 Mux~10102 CAR[5] } { 0.000ns 0.000ns 1.276ns 0.580ns 0.375ns 0.888ns 0.354ns } { 0.000ns 3.066ns 0.459ns 0.087ns 0.459ns 0.459ns 0.583ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.198 ns - Smallest " "Info: - Smallest clock skew is 0.198 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.092 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.092 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { clk } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.772 ns) + CELL(0.560 ns) 3.092 ns CAR\[5\] 2 REG LC_X22_Y34_N9 7 " "Info: 2: + IC(1.772 ns) + CELL(0.560 ns) = 3.092 ns; Loc. = LC_X22_Y34_N9; Fanout = 7; REG Node = 'CAR\[5\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.332 ns" { clk CAR[5] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 42.69 % ) " "Info: Total cell delay = 1.320 ns ( 42.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.772 ns ( 57.31 % ) " "Info: Total interconnect delay = 1.772 ns ( 57.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.092 ns" { clk CAR[5] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "3.092 ns" { clk clk~out0 CAR[5] } { 0.000ns 0.000ns 1.772ns } { 0.000ns 0.760ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.894 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.894 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { clk } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.787 ns) + CELL(0.347 ns) 2.894 ns lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|ram_block1a1~porta_address_reg0 2 MEM M512_X20_Y35 2 " "Info: 2: + IC(1.787 ns) + CELL(0.347 ns) = 2.894 ns; Loc. = M512_X20_Y35; Fanout = 2; MEM Node = 'lpm_rom:U5\|altrom:srom\|altsyncram:rom_block\|altsyncram_vcp:auto_generated\|ram_block1a1~porta_address_reg0'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.134 ns" { clk lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_vcp.tdf" "" { Text "E:/workspace/project/db/altsyncram_vcp.tdf" 62 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.107 ns ( 38.25 % ) " "Info: Total cell delay = 1.107 ns ( 38.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.787 ns ( 61.75 % ) " "Info: Total interconnect delay = 1.787 ns ( 61.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.894 ns" { clk lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "2.894 ns" { clk clk~out0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 } { 0.000ns 0.000ns 1.787ns } { 0.000ns 0.760ns 0.347ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.092 ns" { clk CAR[5] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "3.092 ns" { clk clk~out0 CAR[5] } { 0.000ns 0.000ns 1.772ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.894 ns" { clk lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "2.894 ns" { clk clk~out0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 } { 0.000ns 0.000ns 1.787ns } { 0.000ns 0.760ns 0.347ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.519 ns + " "Info: + Micro clock to output delay of source is 0.519 ns" { } { { "db/altsyncram_vcp.tdf" "" { Text "E:/workspace/project/db/altsyncram_vcp.tdf" 62 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "8.586 ns" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] CAR[1]~2003 CAR[1]~2008 Mux~10094 Mux~10102 CAR[5] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "8.586 ns" { lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] CAR[1]~2003 CAR[1]~2008 Mux~10094 Mux~10102 CAR[5] } { 0.000ns 0.000ns 1.276ns 0.580ns 0.375ns 0.888ns 0.354ns } { 0.000ns 3.066ns 0.459ns 0.087ns 0.459ns 0.459ns 0.583ns } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.092 ns" { clk CAR[5] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "3.092 ns" { clk clk~out0 CAR[5] } { 0.000ns 0.000ns 1.772ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.894 ns" { clk lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "2.894 ns" { clk clk~out0 lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ram_block1a1~porta_address_reg0 } { 0.000ns 0.000ns 1.787ns } { 0.000ns 0.760ns 0.347ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "CAR\[1\] IR\[4\] clk 10.854 ns register " "Info: tsu for register \"CAR\[1\]\" (data pin = \"IR\[4\]\", clock pin = \"clk\") is 10.854 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.936 ns + Longest pin register " "Info: + Longest pin to register delay is 13.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns IR\[4\] 1 PIN PIN_AB10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_AB10; Fanout = 4; PIN Node = 'IR\[4\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { IR[4] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.621 ns) + CELL(0.213 ns) 6.975 ns Mux~10072 2 COMB LC_X22_Y35_N8 8 " "Info: 2: + IC(5.621 ns) + CELL(0.213 ns) = 6.975 ns; Loc. = LC_X22_Y35_N8; Fanout = 8; COMB Node = 'Mux~10072'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "5.834 ns" { IR[4] Mux~10072 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.332 ns) 8.003 ns Mux~10088 3 COMB LC_X23_Y35_N8 7 " "Info: 3: + IC(0.696 ns) + CELL(0.332 ns) = 8.003 ns; Loc. = LC_X23_Y35_N8; Fanout = 7; COMB Node = 'Mux~10088'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "1.028 ns" { Mux~10072 Mux~10088 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.946 ns) + CELL(0.459 ns) 9.408 ns CAR\[1\]~2013 4 COMB LC_X25_Y35_N1 1 " "Info: 4: + IC(0.946 ns) + CELL(0.459 ns) = 9.408 ns; Loc. = LC_X25_Y35_N1; Fanout = 1; COMB Node = 'CAR\[1\]~2013'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "1.405 ns" { Mux~10088 CAR[1]~2013 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.335 ns) + CELL(0.332 ns) 10.075 ns CAR\[1\]~2014 5 COMB LC_X25_Y35_N2 1 " "Info: 5: + IC(0.335 ns) + CELL(0.332 ns) = 10.075 ns; Loc. = LC_X25_Y35_N2; Fanout = 1; COMB Node = 'CAR\[1\]~2014'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "0.667 ns" { CAR[1]~2013 CAR[1]~2014 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.919 ns) + CELL(0.332 ns) 12.326 ns CAR\[1\]~2015 6 COMB LC_X23_Y34_N5 3 " "Info: 6: + IC(1.919 ns) + CELL(0.332 ns) = 12.326 ns; Loc. = LC_X23_Y34_N5; Fanout = 3; COMB Node = 'CAR\[1\]~2015'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.251 ns" { CAR[1]~2014 CAR[1]~2015 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.884 ns) + CELL(0.726 ns) 13.936 ns CAR\[1\] 7 REG LC_X24_Y34_N8 7 " "Info: 7: + IC(0.884 ns) + CELL(0.726 ns) = 13.936 ns; Loc. = LC_X24_Y34_N8; Fanout = 7; REG Node = 'CAR\[1\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "1.610 ns" { CAR[1]~2015 CAR[1] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.535 ns ( 25.37 % ) " "Info: Total cell delay = 3.535 ns ( 25.37 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.401 ns ( 74.63 % ) " "Info: Total interconnect delay = 10.401 ns ( 74.63 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "13.936 ns" { IR[4] Mux~10072 Mux~10088 CAR[1]~2013 CAR[1]~2014 CAR[1]~2015 CAR[1] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "13.936 ns" { IR[4] IR[4]~out0 Mux~10072 Mux~10088 CAR[1]~2013 CAR[1]~2014 CAR[1]~2015 CAR[1] } { 0.000ns 0.000ns 5.621ns 0.696ns 0.946ns 0.335ns 1.919ns 0.884ns } { 0.000ns 1.141ns 0.213ns 0.332ns 0.459ns 0.332ns 0.332ns 0.726ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.092 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.092 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { clk } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.772 ns) + CELL(0.560 ns) 3.092 ns CAR\[1\] 2 REG LC_X24_Y34_N8 7 " "Info: 2: + IC(1.772 ns) + CELL(0.560 ns) = 3.092 ns; Loc. = LC_X24_Y34_N8; Fanout = 7; REG Node = 'CAR\[1\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.332 ns" { clk CAR[1] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 42.69 % ) " "Info: Total cell delay = 1.320 ns ( 42.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.772 ns ( 57.31 % ) " "Info: Total interconnect delay = 1.772 ns ( 57.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.092 ns" { clk CAR[1] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "3.092 ns" { clk clk~out0 CAR[1] } { 0.000ns 0.000ns 1.772ns } { 0.000ns 0.760ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "13.936 ns" { IR[4] Mux~10072 Mux~10088 CAR[1]~2013 CAR[1]~2014 CAR[1]~2015 CAR[1] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "13.936 ns" { IR[4] IR[4]~out0 Mux~10072 Mux~10088 CAR[1]~2013 CAR[1]~2014 CAR[1]~2015 CAR[1] } { 0.000ns 0.000ns 5.621ns 0.696ns 0.946ns 0.335ns 1.919ns 0.884ns } { 0.000ns 1.141ns 0.213ns 0.332ns 0.459ns 0.332ns 0.332ns 0.726ns } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.092 ns" { clk CAR[1] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "3.092 ns" { clk clk~out0 CAR[1] } { 0.000ns 0.000ns 1.772ns } { 0.000ns 0.760ns 0.560ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk control_signal\[2\] control_signal\[2\]~reg0 8.440 ns register " "Info: tco from clock \"clk\" to destination pin \"control_signal\[2\]\" through register \"control_signal\[2\]~reg0\" is 8.440 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.107 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { clk } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.787 ns) + CELL(0.560 ns) 3.107 ns control_signal\[2\]~reg0 2 REG LC_X25_Y35_N9 1 " "Info: 2: + IC(1.787 ns) + CELL(0.560 ns) = 3.107 ns; Loc. = LC_X25_Y35_N9; Fanout = 1; REG Node = 'control_signal\[2\]~reg0'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.347 ns" { clk control_signal[2]~reg0 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 42.48 % ) " "Info: Total cell delay = 1.320 ns ( 42.48 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.787 ns ( 57.52 % ) " "Info: Total interconnect delay = 1.787 ns ( 57.52 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.107 ns" { clk control_signal[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "3.107 ns" { clk clk~out0 control_signal[2]~reg0 } { 0.000ns 0.000ns 1.787ns } { 0.000ns 0.760ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.157 ns + Longest register pin " "Info: + Longest register to pin delay is 5.157 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control_signal\[2\]~reg0 1 REG LC_X25_Y35_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y35_N9; Fanout = 1; REG Node = 'control_signal\[2\]~reg0'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { control_signal[2]~reg0 } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.653 ns) + CELL(2.504 ns) 5.157 ns control_signal\[2\] 2 PIN PIN_AE11 0 " "Info: 2: + IC(2.653 ns) + CELL(2.504 ns) = 5.157 ns; Loc. = PIN_AE11; Fanout = 0; PIN Node = 'control_signal\[2\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "5.157 ns" { control_signal[2]~reg0 control_signal[2] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.504 ns ( 48.56 % ) " "Info: Total cell delay = 2.504 ns ( 48.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.653 ns ( 51.44 % ) " "Info: Total interconnect delay = 2.653 ns ( 51.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "5.157 ns" { control_signal[2]~reg0 control_signal[2] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "5.157 ns" { control_signal[2]~reg0 control_signal[2] } { 0.000ns 2.653ns } { 0.000ns 2.504ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.107 ns" { clk control_signal[2]~reg0 } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "3.107 ns" { clk clk~out0 control_signal[2]~reg0 } { 0.000ns 0.000ns 1.787ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "5.157 ns" { control_signal[2]~reg0 control_signal[2] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "5.157 ns" { control_signal[2]~reg0 control_signal[2] } { 0.000ns 2.653ns } { 0.000ns 2.504ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "CAR\[6\] flag\[7\] clk -2.880 ns register " "Info: th for register \"CAR\[6\]\" (data pin = \"flag\[7\]\", clock pin = \"clk\") is -2.880 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.092 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.092 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_M24 48 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_M24; Fanout = 48; CLK Node = 'clk'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { clk } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.772 ns) + CELL(0.560 ns) 3.092 ns CAR\[6\] 2 REG LC_X23_Y34_N9 7 " "Info: 2: + IC(1.772 ns) + CELL(0.560 ns) = 3.092 ns; Loc. = LC_X23_Y34_N9; Fanout = 7; REG Node = 'CAR\[6\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "2.332 ns" { clk CAR[6] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 42.69 % ) " "Info: Total cell delay = 1.320 ns ( 42.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.772 ns ( 57.31 % ) " "Info: Total interconnect delay = 1.772 ns ( 57.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.092 ns" { clk CAR[6] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "3.092 ns" { clk clk~out0 CAR[6] } { 0.000ns 0.000ns 1.772ns } { 0.000ns 0.760ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.072 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.072 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns flag\[7\] 1 PIN PIN_K6 7 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K6; Fanout = 7; PIN Node = 'flag\[7\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "" { flag[7] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.413 ns) + CELL(0.364 ns) 6.072 ns CAR\[6\] 2 REG LC_X23_Y34_N9 7 " "Info: 2: + IC(4.413 ns) + CELL(0.364 ns) = 6.072 ns; Loc. = LC_X23_Y34_N9; Fanout = 7; REG Node = 'CAR\[6\]'" { } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "4.777 ns" { flag[7] CAR[6] } "NODE_NAME" } "" } } { "controlunit.vhd" "" { Text "E:/workspace/project/controlunit.vhd" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.659 ns ( 27.32 % ) " "Info: Total cell delay = 1.659 ns ( 27.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.413 ns ( 72.68 % ) " "Info: Total interconnect delay = 4.413 ns ( 72.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "6.072 ns" { flag[7] CAR[6] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "6.072 ns" { flag[7] flag[7]~out0 CAR[6] } { 0.000ns 0.000ns 4.413ns } { 0.000ns 1.295ns 0.364ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "3.092 ns" { clk CAR[6] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "3.092 ns" { clk clk~out0 CAR[6] } { 0.000ns 0.000ns 1.772ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/program files/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controlunit" "UNKNOWN" "V1" "E:/workspace/project/db/cpu.quartus_db" { Floorplan "E:/workspace/project/" "" "6.072 ns" { flag[7] CAR[6] } "NODE_NAME" } "" } } { "d:/program files/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus51/bin/Technology_Viewer.qrui" "6.072 ns" { flag[7] flag[7]~out0 CAR[6] } { 0.000ns 0.000ns 4.413ns } { 0.000ns 1.295ns 0.364ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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