controlunit.sim.rpt

CPU设计中的controlunit源码

+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      43.90 % ;
; Total nodes checked                                 ; 112          ;
; Total output ports checked                          ; 123          ;
; Total output ports with complete 1/0-value coverage ; 54           ;
; Total output ports with no 1/0-value coverage       ; 69           ;
; Total output ports with no 1-value coverage         ; 69           ;
; Total output ports with no 0-value coverage         ; 69           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                      ;
+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                     ; Output Port Name                                                                              ; Output Port Type ;
+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------------+
; |controlunit|control_signal[0]~reg0                                                           ; |controlunit|control_signal[0]~reg0                                                           ; regout           ;
; |controlunit|control_signal[1]~reg0                                                           ; |controlunit|control_signal[1]~reg0                                                           ; regout           ;
; |controlunit|control_signal[2]~reg0                                                           ; |controlunit|control_signal[2]~reg0                                                           ; regout           ;
; |controlunit|control_signal[3]~reg0                                                           ; |controlunit|control_signal[3]~reg0                                                           ; regout           ;
; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[0] ; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[0] ; portadataout0    ;
; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[1] ; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[1] ; portadataout0    ;
; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[2] ; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[2] ; portadataout0    ;
; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[2] ; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[3] ; portadataout1    ;
; |controlunit|CAR[0]                                                                           ; |controlunit|CAR[0]                                                                           ; regout           ;
; |controlunit|CAR[1]                                                                           ; |controlunit|CAR[1]                                                                           ; regout           ;
; |controlunit|CAR[2]                                                                           ; |controlunit|CAR[2]                                                                           ; regout           ;
; |controlunit|CAR[3]                                                                           ; |controlunit|CAR[3]                                                                           ; regout           ;
; |controlunit|Mux~10068                                                                        ; |controlunit|Mux~10068                                                                        ; combout          ;
; |controlunit|Mux~10069                                                                        ; |controlunit|Mux~10069                                                                        ; combout          ;
; |controlunit|Mux~10070                                                                        ; |controlunit|Mux~10070                                                                        ; combout          ;
; |controlunit|Mux~10071                                                                        ; |controlunit|Mux~10071                                                                        ; combout          ;
; |controlunit|Mux~10081                                                                        ; |controlunit|Mux~10081                                                                        ; combout          ;
; |controlunit|add~121                                                                          ; |controlunit|add~121                                                                          ; combout          ;
; |controlunit|add~121                                                                          ; |controlunit|add~123                                                                          ; cout0            ;
; |controlunit|add~121                                                                          ; |controlunit|add~123COUT1_162                                                                 ; cout1            ;
; |controlunit|Mux~10083                                                                        ; |controlunit|Mux~10083                                                                        ; combout          ;
; |controlunit|Mux~10084                                                                        ; |controlunit|Mux~10084                                                                        ; combout          ;
; |controlunit|add~126                                                                          ; |controlunit|add~126                                                                          ; combout          ;
; |controlunit|add~126                                                                          ; |controlunit|add~128                                                                          ; cout0            ;
; |controlunit|add~126                                                                          ; |controlunit|add~128COUT1_163                                                                 ; cout1            ;
; |controlunit|Mux~10087                                                                        ; |controlunit|Mux~10087                                                                        ; combout          ;
; |controlunit|Mux~10089                                                                        ; |controlunit|Mux~10089                                                                        ; combout          ;
; |controlunit|CAR[1]~2005                                                                      ; |controlunit|CAR[1]~2005                                                                      ; combout          ;
; |controlunit|CAR[1]~2006                                                                      ; |controlunit|CAR[1]~2006                                                                      ; combout          ;
; |controlunit|CAR[1]~2007                                                                      ; |controlunit|CAR[1]~2007                                                                      ; combout          ;
; |controlunit|CAR[1]~2008                                                                      ; |controlunit|CAR[1]~2008                                                                      ; combout          ;
; |controlunit|CAR[1]~2009                                                                      ; |controlunit|CAR[1]~2009                                                                      ; combout          ;
; |controlunit|CAR[1]~2010                                                                      ; |controlunit|CAR[1]~2010                                                                      ; combout          ;
; |controlunit|CAR[1]~2011                                                                      ; |controlunit|CAR[1]~2011                                                                      ; combout          ;
; |controlunit|add~131                                                                          ; |controlunit|add~131                                                                          ; combout          ;
; |controlunit|add~131                                                                          ; |controlunit|add~133                                                                          ; cout0            ;
; |controlunit|add~131                                                                          ; |controlunit|add~133COUT1_164                                                                 ; cout1            ;
; |controlunit|Mux~10092                                                                        ; |controlunit|Mux~10092                                                                        ; combout          ;
; |controlunit|CAR[1]~2016                                                                      ; |controlunit|CAR[1]~2016                                                                      ; combout          ;
; |controlunit|Mux~10094                                                                        ; |controlunit|Mux~10094                                                                        ; combout          ;
; |controlunit|add~136                                                                          ; |controlunit|add~136                                                                          ; combout          ;
; |controlunit|add~136                                                                          ; |controlunit|add~138                                                                          ; cout0            ;
; |controlunit|add~136                                                                          ; |controlunit|add~138COUT1                                                                     ; cout1            ;
; |controlunit|Mux~10098                                                                        ; |controlunit|Mux~10098                                                                        ; combout          ;
; |controlunit|add~141                                                                          ; |controlunit|add~141                                                                          ; combout          ;
; |controlunit|CAR[4]~2017                                                                      ; |controlunit|CAR[4]~2017                                                                      ; combout          ;
; |controlunit|CAR[4]~2018                                                                      ; |controlunit|CAR[4]~2018                                                                      ; combout          ;
; |controlunit|Mux~10099                                                                        ; |controlunit|Mux~10099                                                                        ; combout          ;
; |controlunit|CAR[1]~2025                                                                      ; |controlunit|CAR[1]~2025                                                                      ; combout          ;
; |controlunit|clk                                                                              ; |controlunit|clk                                                                              ; combout          ;
; |controlunit|control_signal[0]                                                                ; |controlunit|control_signal[0]                                                                ; padio            ;
; |controlunit|control_signal[1]                                                                ; |controlunit|control_signal[1]                                                                ; padio            ;
; |controlunit|control_signal[2]                                                                ; |controlunit|control_signal[2]                                                                ; padio            ;
; |controlunit|control_signal[3]                                                                ; |controlunit|control_signal[3]                                                                ; padio            ;
+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                         ;
+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                     ; Output Port Name                                                                              ; Output Port Type ;
+-----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+------------------+
; |controlunit|control_signal[4]~reg0                                                           ; |controlunit|control_signal[4]~reg0                                                           ; regout           ;
; |controlunit|control_signal[5]~reg0                                                           ; |controlunit|control_signal[5]~reg0                                                           ; regout           ;
; |controlunit|control_signal[6]~reg0                                                           ; |controlunit|control_signal[6]~reg0                                                           ; regout           ;
; |controlunit|control_signal[7]~reg0                                                           ; |controlunit|control_signal[7]~reg0                                                           ; regout           ;
; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[0] ; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[6] ; portadataout1    ;