controlunit.map.eqn

CPU设计中的controlunit源码

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--A1L51Q is control_signal[0]~reg0
--operation mode is normal

A1L51Q_lut_out = E1_q_a[0];
A1L51Q = DFFEAS(A1L51Q_lut_out, clk, VCC, , , , , , );


--A1L53Q is control_signal[1]~reg0
--operation mode is normal

A1L53Q_lut_out = E1_q_a[1];
A1L53Q = DFFEAS(A1L53Q_lut_out, clk, VCC, , , , , , );


--A1L55Q is control_signal[2]~reg0
--operation mode is normal

A1L55Q_lut_out = E1_q_a[2];
A1L55Q = DFFEAS(A1L55Q_lut_out, clk, VCC, , , , , , );


--A1L57Q is control_signal[3]~reg0
--operation mode is normal

A1L57Q_lut_out = E1_q_a[3];
A1L57Q = DFFEAS(A1L57Q_lut_out, clk, VCC, , , , , , );


--A1L59Q is control_signal[4]~reg0
--operation mode is normal

A1L59Q_lut_out = E1_q_a[4];
A1L59Q = DFFEAS(A1L59Q_lut_out, clk, VCC, , , , , , );


--A1L61Q is control_signal[5]~reg0
--operation mode is normal

A1L61Q_lut_out = E1_q_a[5];
A1L61Q = DFFEAS(A1L61Q_lut_out, clk, VCC, , , , , , );


--A1L63Q is control_signal[6]~reg0
--operation mode is normal

A1L63Q_lut_out = E1_q_a[6];
A1L63Q = DFFEAS(A1L63Q_lut_out, clk, VCC, , , , , , );


--A1L65Q is control_signal[7]~reg0
--operation mode is normal

A1L65Q_lut_out = E1_q_a[7];
A1L65Q = DFFEAS(A1L65Q_lut_out, clk, VCC, , , , , , );


--E1_q_a[0] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = clk;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];


--E1_q_a[1] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[1]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = clk;
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out[0];


--E1_q_a[2] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[2]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_clock_0 = clk;
E1_q_a[2]_PORT_A_data_out = MEMORY(, , E1_q_a[2]_PORT_A_address_reg, , , , , , E1_q_a[2]_clock_0, , , , , );
E1_q_a[2] = E1_q_a[2]_PORT_A_data_out[0];


--E1_q_a[3] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[3]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[3]_PORT_A_address_reg = DFFE(E1_q_a[3]_PORT_A_address, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_clock_0 = clk;
E1_q_a[3]_PORT_A_data_out = MEMORY(, , E1_q_a[3]_PORT_A_address_reg, , , , , , E1_q_a[3]_clock_0, , , , , );
E1_q_a[3] = E1_q_a[3]_PORT_A_data_out[0];


--E1_q_a[4] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[4]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_clock_0 = clk;
E1_q_a[4]_PORT_A_data_out = MEMORY(, , E1_q_a[4]_PORT_A_address_reg, , , , , , E1_q_a[4]_clock_0, , , , , );
E1_q_a[4] = E1_q_a[4]_PORT_A_data_out[0];


--E1_q_a[5] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[5]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[5]_PORT_A_address_reg = DFFE(E1_q_a[5]_PORT_A_address, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_clock_0 = clk;
E1_q_a[5]_PORT_A_data_out = MEMORY(, , E1_q_a[5]_PORT_A_address_reg, , , , , , E1_q_a[5]_clock_0, , , , , );
E1_q_a[5] = E1_q_a[5]_PORT_A_data_out[0];


--E1_q_a[6] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[6]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[6]_PORT_A_address_reg = DFFE(E1_q_a[6]_PORT_A_address, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_clock_0 = clk;
E1_q_a[6]_PORT_A_data_out = MEMORY(, , E1_q_a[6]_PORT_A_address_reg, , , , , , E1_q_a[6]_clock_0, , , , , );
E1_q_a[6] = E1_q_a[6]_PORT_A_data_out[0];


--E1_q_a[7] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[7]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = clk;
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7] = E1_q_a[7]_PORT_A_data_out[0];


--CAR[0] is CAR[0]
--operation mode is normal

CAR[0]_lut_out = A1L99 # A1L100 # A1L102 # A1L103;
CAR[0] = DFFEAS(CAR[0]_lut_out, clk, VCC, , , , , , );


--CAR[1] is CAR[1]
--operation mode is normal

CAR[1]_lut_out = A1L25 & A1L3 # !A1L25 & (E1_q_a[6] # A1L106);
CAR[1] = DFFEAS(CAR[1]_lut_out, clk, VCC, , A1L31, , , , );


--CAR[2] is CAR[2]
--operation mode is normal

CAR[2]_lut_out = A1L108 # A1L109 & A1L110;
CAR[2] = DFFEAS(CAR[2]_lut_out, clk, VCC, , A1L31, , , , );


--CAR[3] is CAR[3]
--operation mode is normal

CAR[3]_lut_out = A1L113 # A1L110 & (A1L117 # A1L119);
CAR[3] = DFFEAS(CAR[3]_lut_out, clk, VCC, , A1L31, , , , );


--CAR[4] is CAR[4]
--operation mode is normal

CAR[4]_lut_out = A1L114 # A1L104 & A1L115 & !A1L38;
CAR[4] = DFFEAS(CAR[4]_lut_out, clk, VCC, , A1L41, , , , );


--CAR[5] is CAR[5]
--operation mode is normal

CAR[5]_lut_out = A1L11 & (A1L25 # A1L116 & !E1_q_a[6]) # !A1L11 & (A1L116 & !E1_q_a[6]);
CAR[5] = DFFEAS(CAR[5]_lut_out, clk, VCC, , A1L45, , , , );


--CAR[6] is CAR[6]
--operation mode is normal

CAR[6]_lut_out = A1L38 & A1L13 # !A1L38 & (E1_q_a[2] & !flag[7]);
CAR[6] = DFFEAS(CAR[6]_lut_out, clk, VCC, , A1L41, , , , );


--CAR[7] is CAR[7]
--operation mode is normal

CAR[7]_lut_out = A1L15 & (A1L23 # A1L32 # !A1L24);
CAR[7] = DFFEAS(CAR[7]_lut_out, clk, VCC, , A1L45, , , , );


--A1L86 is Mux~10068
--operation mode is normal

A1L86 = !E1_q_a[2] & !E1_q_a[3];


--A1L19 is CAR[1]~2003
--operation mode is normal

A1L19 = !E1_q_a[4] & !E1_q_a[5] & !E1_q_a[7];


--A1L87 is Mux~10069
--operation mode is normal

A1L87 = E1_q_a[1] & (!E1_q_a[6]);


--A1L20 is CAR[1]~2004
--operation mode is normal

A1L20 = E1_q_a[6] & (!E1_q_a[0] & !E1_q_a[1]);


--A1L88 is Mux~10070
--operation mode is normal

A1L88 = A1L19 & (A1L87 # A1L86 & A1L20);


--A1L89 is Mux~10071
--operation mode is normal

A1L89 = A1L88 & (E1_q_a[0] & (E1_q_a[3] $ !E1_q_a[2]) # !E1_q_a[0] & E1_q_a[3] & !E1_q_a[2]);


--A1L90 is Mux~10072
--operation mode is normal

A1L90 = !IR[6] & !IR[4] & !IR[5] & !IR[7];


--A1L91 is Mux~10073
--operation mode is normal

A1L91 = IR[2] & !IR[1] & (!IR[3] # !IR[0]) # !IR[2] & (IR[3] $ (!IR[0] & IR[1]));


--A1L92 is Mux~10074
--operation mode is normal

A1L92 = IR[2] & (IR[0] & !IR[1] & !IR[3] # !IR[0] & (IR[3])) # !IR[2] & (IR[1] $ (IR[0] & IR[3]));


--A1L93 is Mux~10075
--operation mode is normal

A1L93 = !IR[6] & !IR[4] & !IR[5];


--A1L94 is Mux~10076
--operation mode is normal

A1L94 = IR[3] & (IR[2] $ (IR[0] & IR[1])) # !IR[3] & !IR[2] & (IR[0] # IR[1]);


--A1L95 is Mux~10077
--operation mode is normal

A1L95 = A1L93 & A1L94 & (!IR[7]);


--A1L96 is Mux~10078
--operation mode is normal

A1L96 = A1L90 & A1L91;


--A1L97 is Mux~10079
--operation mode is normal

A1L97 = IR[0] & !IR[3] & (!IR[2] # !IR[1]) # !IR[0] & (IR[2] & (!IR[3]) # !IR[2] & IR[1]);


--A1L98 is Mux~10080
--operation mode is normal

A1L98 = !A1L97 # !A1L90;


--A1L99 is Mux~10081
--operation mode is normal

A1L99 = A1L86 & A1L89 & A1L118 & !E1_q_a[6];


--A1L100 is Mux~10082
--operation mode is normal

A1L100 = E1_q_a[2] & A1L89 & flag[7] & !flag[4];


--A1L1 is add~121
--operation mode is arithmetic

A1L1 = !CAR[0];

--A1L2 is add~123
--operation mode is arithmetic

A1L2 = CARRY(CAR[0]);


--A1L101 is Mux~10083
--operation mode is normal

A1L101 = E1_q_a[0] & (E1_q_a[3] $ !E1_q_a[2]) # !E1_q_a[0] & E1_q_a[3] & !E1_q_a[2];


--A1L102 is Mux~10084
--operation mode is normal

A1L102 = A1L1 & (!E1_q_a[6] & !A1L101 # !A1L88);


--A1L103 is Mux~10085
--operation mode is normal

A1L103 = E1_q_a[6] & A1L88 & (CAR[0] # flag[7]);


--A1L3 is add~126
--operation mode is arithmetic

A1L3_carry_eqn = A1L2;
A1L3 = CAR[1] $ (A1L3_carry_eqn);

--A1L4 is add~128
--operation mode is arithmetic

A1L4 = CARRY(!A1L2 # !CAR[1]);


--A1L104 is Mux~10087
--operation mode is normal

A1L104 = E1_q_a[0] & (!E1_q_a[2]);


--A1L105 is Mux~10088
--operation mode is normal

A1L105 = A1L92 & A1L90;


--A1L106 is Mux~10089
--operation mode is normal

A1L106 = A1L104 & (A1L96 & (A1L105 # A1L98) # !A1L96 & (!A1L98 # !A1L105));


--A1L21 is CAR[1]~2005
--operation mode is normal

A1L21 = E1_q_a[6] & (E1_q_a[0] # E1_q_a[3] # E1_q_a[1]) # !E1_q_a[6] & (!E1_q_a[1]);


--A1L22 is CAR[1]~2006
--operation mode is normal

A1L22 = E1_q_a[0] $ E1_q_a[2];


--A1L23 is CAR[1]~2007
--operation mode is normal

A1L23 = A1L21 # !E1_q_a[3] & !E1_q_a[6] & !A1L22;


--A1L24 is CAR[1]~2008
--operation mode is normal

A1L24 = A1L19 & (E1_q_a[3] # !E1_q_a[2]);


--A1L25 is CAR[1]~2009
--operation mode is normal