controlunit.fit.eqn

CPU设计中的controlunit源码

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--A1L59Q is control_signal[0]~reg0 at LC_X25_Y35_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L59Q_lut_out = GND;
A1L59Q = DFFEAS(A1L59Q_lut_out, GLOBAL(clk), VCC, , , E1_q_a[0], , , VCC);


--A1L61Q is control_signal[1]~reg0 at LC_X19_Y35_N2
--operation mode is normal

A1L61Q_lut_out = E1_q_a[1];
A1L61Q = DFFEAS(A1L61Q_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L63Q is control_signal[2]~reg0 at LC_X25_Y35_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L63Q_lut_out = GND;
A1L63Q = DFFEAS(A1L63Q_lut_out, GLOBAL(clk), VCC, , , E1_q_a[2], , , VCC);


--A1L65Q is control_signal[3]~reg0 at LC_X25_Y35_N4
--operation mode is normal

A1L65Q_lut_out = E1_q_a[3];
A1L65Q = DFFEAS(A1L65Q_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L67Q is control_signal[4]~reg0 at LC_X19_Y38_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L67Q_lut_out = GND;
A1L67Q = DFFEAS(A1L67Q_lut_out, GLOBAL(clk), VCC, , , E1_q_a[4], , , VCC);


--A1L69Q is control_signal[5]~reg0 at LC_X21_Y35_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L69Q_lut_out = GND;
A1L69Q = DFFEAS(A1L69Q_lut_out, GLOBAL(clk), VCC, , , E1_q_a[5], , , VCC);


--A1L71Q is control_signal[6]~reg0 at LC_X25_Y35_N6
--operation mode is normal

A1L71Q_lut_out = E1_q_a[6];
A1L71Q = DFFEAS(A1L71Q_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L73Q is control_signal[7]~reg0 at LC_X21_Y34_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L73Q_lut_out = GND;
A1L73Q = DFFEAS(A1L73Q_lut_out, GLOBAL(clk), VCC, , , E1_q_a[7], , , VCC);


--E1_q_a[0] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[0] at M512_X26_Y34
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 2
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];

--E1_q_a[6] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[6] at M512_X26_Y34
E1_q_a[0]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = GLOBAL(clk);
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[6] = E1_q_a[0]_PORT_A_data_out[1];


--E1_q_a[1] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[1] at M512_X20_Y35
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 2
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[1]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = GLOBAL(clk);
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out[0];

--E1_q_a[5] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[5] at M512_X20_Y35
E1_q_a[1]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = GLOBAL(clk);
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[5] = E1_q_a[1]_PORT_A_data_out[1];


--E1_q_a[2] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[2] at M512_X26_Y35
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 2
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[2]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_clock_0 = GLOBAL(clk);
E1_q_a[2]_PORT_A_data_out = MEMORY(, , E1_q_a[2]_PORT_A_address_reg, , , , , , E1_q_a[2]_clock_0, , , , , );
E1_q_a[2] = E1_q_a[2]_PORT_A_data_out[0];

--E1_q_a[3] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[3] at M512_X26_Y35
E1_q_a[2]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_clock_0 = GLOBAL(clk);
E1_q_a[2]_PORT_A_data_out = MEMORY(, , E1_q_a[2]_PORT_A_address_reg, , , , , , E1_q_a[2]_clock_0, , , , , );
E1_q_a[3] = E1_q_a[2]_PORT_A_data_out[1];


--E1_q_a[4] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[4] at M512_X20_Y34
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 2
--Port A Logical Depth: 256, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[4]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_clock_0 = GLOBAL(clk);
E1_q_a[4]_PORT_A_data_out = MEMORY(, , E1_q_a[4]_PORT_A_address_reg, , , , , , E1_q_a[4]_clock_0, , , , , );
E1_q_a[4] = E1_q_a[4]_PORT_A_data_out[0];

--E1_q_a[7] is lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|q_a[7] at M512_X20_Y34
E1_q_a[4]_PORT_A_address = BUS(CAR[0], CAR[1], CAR[2], CAR[3], CAR[4], CAR[5], CAR[6], CAR[7]);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_clock_0 = GLOBAL(clk);
E1_q_a[4]_PORT_A_data_out = MEMORY(, , E1_q_a[4]_PORT_A_address_reg, , , , , , E1_q_a[4]_clock_0, , , , , );
E1_q_a[7] = E1_q_a[4]_PORT_A_data_out[1];


--CAR[0] is CAR[0] at LC_X27_Y34_N0
--operation mode is normal

CAR[0]_lut_out = A1L108 # A1L107 # A1L111 # A1L110;
CAR[0] = DFFEAS(CAR[0]_lut_out, GLOBAL(clk), VCC, , , , , , );


--CAR[1] is CAR[1] at LC_X24_Y34_N8
--operation mode is normal

CAR[1]_lut_out = A1L33 & A1L4 # !A1L33 & (E1_q_a[6] # A1L114);
CAR[1] = DFFEAS(CAR[1]_lut_out, GLOBAL(clk), VCC, , A1L39, , , , );


--CAR[2] is CAR[2] at LC_X24_Y34_N2
--operation mode is normal

CAR[2]_lut_out = A1L116 # A1L118 & A1L117;
CAR[2] = DFFEAS(CAR[2]_lut_out, GLOBAL(clk), VCC, , A1L39, , , , );


--CAR[3] is CAR[3] at LC_X24_Y34_N5
--operation mode is normal

CAR[3]_lut_out = A1L121 # A1L118 & (A1L125 # A1L127);
CAR[3] = DFFEAS(CAR[3]_lut_out, GLOBAL(clk), VCC, , A1L39, , , , );


--CAR[4] is CAR[4] at LC_X25_Y34_N3
--operation mode is normal

CAR[4]_lut_out = A1L122 # A1L123 & A1L112 & !A1L46;
CAR[4] = DFFEAS(CAR[4]_lut_out, GLOBAL(clk), VCC, , A1L49, , , , );


--CAR[5] is CAR[5] at LC_X22_Y34_N9
--operation mode is normal

CAR[5]_lut_out = A1L124 & (A1L33 & A1L17 # !E1_q_a[6]) # !A1L124 & A1L33 & (A1L17);
CAR[5] = DFFEAS(CAR[5]_lut_out, GLOBAL(clk), VCC, , A1L53, , , , );


--CAR[6] is CAR[6] at LC_X23_Y34_N9
--operation mode is normal

CAR[6]_lut_out = A1L46 & (A1L20) # !A1L46 & E1_q_a[2] & !flag[7];
CAR[6] = DFFEAS(CAR[6]_lut_out, GLOBAL(clk), VCC, , A1L49, , , , );


--CAR[7] is CAR[7] at LC_X25_Y35_N7
--operation mode is normal

CAR[7]_lut_out = A1L23 & (A1L40 # A1L31 # !A1L32);
CAR[7] = DFFEAS(CAR[7]_lut_out, GLOBAL(clk), VCC, , A1L53, , , , );


--A1L94 is Mux~10068 at LC_X27_Y34_N3
--operation mode is normal

A1L94 = !E1_q_a[2] & !E1_q_a[3];


--A1L27 is CAR[1]~2003 at LC_X25_Y34_N5
--operation mode is normal

A1L27 = !E1_q_a[5] & !E1_q_a[4] & !E1_q_a[7];


--A1L95 is Mux~10069 at LC_X27_Y34_N9
--operation mode is normal

A1L95 = !E1_q_a[6] & (E1_q_a[1]);


--A1L28 is CAR[1]~2004 at LC_X23_Y34_N6
--operation mode is normal

A1L28 = !E1_q_a[0] & E1_q_a[6] & !E1_q_a[1];


--A1L96 is Mux~10070 at LC_X27_Y34_N4
--operation mode is normal

A1L96 = A1L27 & (A1L95 # A1L94 & A1L28);


--A1L97 is Mux~10071 at LC_X27_Y34_N1
--operation mode is normal

A1L97 = A1L96 & (E1_q_a[3] & (E1_q_a[0] $ !E1_q_a[2]) # !E1_q_a[3] & E1_q_a[0] & !E1_q_a[2]);


--A1L98 is Mux~10072 at LC_X22_Y35_N8
--operation mode is normal

A1L98 = !IR[7] & !IR[6] & !IR[4] & !IR[5];


--A1L99 is Mux~10073 at LC_X22_Y35_N1
--operation mode is normal

A1L99 = IR[2] & !IR[1] & (!IR[3] # !IR[0]) # !IR[2] & (IR[3] $ (!IR[0] & IR[1]));


--A1L100 is Mux~10074 at LC_X22_Y35_N5
--operation mode is normal

A1L100 = IR[3] & (IR[0] $ (IR[2] # IR[1])) # !IR[3] & (IR[2] & IR[0] & !IR[1] # !IR[2] & (IR[1]));


--A1L101 is Mux~10075 at LC_X22_Y35_N7
--operation mode is normal

A1L101 = !IR[6] & !IR[4] & !IR[5];


--A1L102 is Mux~10076 at LC_X22_Y35_N6
--operation mode is normal

A1L102 = IR[3] & (IR[2] $ (IR[0] & IR[1])) # !IR[3] & !IR[2] & (IR[0] # IR[1]);


--A1L103 is Mux~10077 at LC_X23_Y35_N4
--operation mode is normal

A1L103 = A1L102 & !IR[7] & A1L101;


--A1L104 is Mux~10078 at LC_X23_Y35_N6
--operation mode is normal

A1L104 = A1L98 & (A1L99);


--A1L105 is Mux~10079 at LC_X22_Y35_N4
--operation mode is normal

A1L105 = IR[0] & !IR[3] & (!IR[1] # !IR[2]) # !IR[0] & (IR[2] & !IR[3] # !IR[2] & (IR[1]));


--A1L106 is Mux~10080 at LC_X23_Y35_N0
--operation mode is normal

A1L106 = !A1L105 # !A1L98;


--A1L107 is Mux~10081 at LC_X27_Y34_N6
--operation mode is normal

A1L107 = A1L94 & !E1_q_a[6] & A1L97 & A1L126;


--A1L108 is Mux~10082 at LC_X27_Y34_N8
--operation mode is normal

A1L108 = !flag[4] & A1L97 & E1_q_a[2] & flag[7];


--A1L1 is add~121 at LC_X22_Y34_N0
--operation mode is arithmetic

A1L1 = !CAR[0];

--A1L2 is add~123 at LC_X22_Y34_N0
--operation mode is arithmetic

A1L2_cout_0 = CAR[0];
A1L2 = CARRY(A1L2_cout_0);

--A1L3 is add~123COUT1_162 at LC_X22_Y34_N0
--operation mode is arithmetic

A1L3_cout_1 = CAR[0];
A1L3 = CARRY(A1L3_cout_1);


--A1L109 is Mux~10083 at LC_X27_Y34_N5
--operation mode is normal

A1L109 = E1_q_a[2] & (E1_q_a[0] & E1_q_a[3]) # !E1_q_a[2] & (E1_q_a[0] $ E1_q_a[3]);


--A1L110 is Mux~10084 at LC_X27_Y34_N2
--operation mode is normal

A1L110 = A1L1 & (!E1_q_a[6] & !A1L109 # !A1L96);


--A1L111 is Mux~10085 at LC_X27_Y34_N7
--operation mode is normal

A1L111 = A1L96 & E1_q_a[6] & (flag[7] # CAR[0]);


--A1L4 is add~126 at LC_X22_Y34_N1
--operation mode is arithmetic

A1L4 = CAR[1] $ A1L2;

--A1L5 is add~128 at LC_X22_Y34_N1
--operation mode is arithmetic

A1L5_cout_0 = !A1L2 # !CAR[1];
A1L5 = CARRY(A1L5_cout_0);

--A1L6 is add~128COUT1_163 at LC_X22_Y34_N1
--operation mode is arithmetic

A1L6_cout_1 = !A1L3 # !CAR[1];
A1L6 = CARRY(A1L6_cout_1);


--A1L112 is Mux~10087 at LC_X24_Y34_N6
--operation mode is normal

A1L112 = !E1_q_a[2] & (E1_q_a[0]);


--A1L113 is Mux~10088 at LC_X23_Y35_N8
--operation mode is normal

A1L113 = A1L98 & (A1L100);


--A1L114 is Mux~10089 at LC_X24_Y34_N7
--operation mode is normal

A1L114 = A1L112 & (A1L104 & (A1L106 # A1L113) # !A1L104 & (!A1L113 # !A1L106));


--A1L29 is CAR[1]~2005 at LC_X25_Y34_N6
--operation mode is normal

A1L29 = E1_q_a[1] & (E1_q_a[6]) # !E1_q_a[1] & (E1_q_a[0] # E1_q_a[3] # !E1_q_a[6]);


--A1L30 is CAR[1]~2006 at LC_X25_Y34_N9
--operation mode is normal

A1L30 = E1_q_a[2] $ (E1_q_a[0]);


--A1L31 is CAR[1]~2007 at LC_X25_Y34_N2
--operation mode is normal

A1L31 = A1L29 # !E1_q_a[6] & !E1_q_a[3] & !A1L30;


--A1L32 is CAR[1]~2008 at LC_X25_Y34_N7
--operation mode is normal

A1L32 = A1L27 & (E1_q_a[3] # !E1_q_a[2]);


--A1L33 is CAR[1]~2009 at LC_X25_Y34_N8
--operation mode is normal

A1L33 = A1L31 # A1L30 & E1_q_a[3] # !A1L32;


--A1L34 is CAR[1]~2010 at LC_X23_Y34_N7
--operation mode is normal

A1L34 = E1_q_a[0] & !E1_q_a[6] & E1_q_a[1];


--A1L35 is CAR[1]~2011 at LC_X23_Y34_N4
--operation mode is normal

A1L35 = A1L94 & A1L27 & (A1L28 # A1L34);