📄 controlunit.map.rpt
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; Total logic cells in carry chains ; 8 ;
; I/O pins ; 25 ;
; Total memory bits ; 2048 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 24 ;
; Total fan-out ; 362 ;
; Average fan-out ; 3.12 ;
+---------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+---------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------+
; |controlunit ; 83 (83) ; 16 ; 2048 ; 0 ; 0 ; 0 ; 0 ; 25 ; 0 ; 67 (67) ; 8 (8) ; 8 (8) ; 8 (8) ; 0 (0) ; |controlunit ;
; |lpm_rom:U5| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |controlunit|lpm_rom:U5 ;
; |altrom:srom| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |controlunit|lpm_rom:U5|altrom:srom ;
; |altsyncram:rom_block| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block ;
; |altsyncram_vcp:auto_generated| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |controlunit|lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated ;
+---------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+-----------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+-----------------+
; lpm_rom:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 256 ; 8 ; -- ; -- ; 2048 ; controlunit.mif ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+-----------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 16 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 7 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 272:1 ; 2 bits ; 362 LEs ; 16 LEs ; 346 LEs ; Yes ; |controlunit|CAR[5] ;
; 272:1 ; 2 bits ; 362 LEs ; 16 LEs ; 346 LEs ; Yes ; |controlunit|CAR[4] ;
; 272:1 ; 3 bits ; 543 LEs ; 30 LEs ; 513 LEs ; Yes ; |controlunit|CAR[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+--------------------------------------------------------------------------------------------------+
; Source assignments for LPM_ROM:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------+
; Assignment ; Value ; from ; to ;
+---------------------------------+--------------------+------+------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------------+
+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: LPM_ROM:U5 ;
+------------------------+-----------------+----------------+
; Parameter Name ; Value ; Type ;
+------------------------+-----------------+----------------+
; LPM_WIDTH ; 8 ; Integer ;
; LPM_WIDTHAD ; 8 ; Integer ;
; LPM_NUMWORDS ; 0 ; Integer ;
; LPM_ADDRESS_CONTROL ; REGISTERED ; Untyped ;
; LPM_OUTDATA ; UNREGISTERED ; Untyped ;
; LPM_FILE ; controlunit.mif ; Untyped ;
; DEVICE_FAMILY ; Stratix ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-----------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/workspace/project/controlunit.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Apr 18 08:50:37 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu -c controlunit
Info: Found 3 design units, including 1 entities, in source file controlunit.vhd
Info: Found design unit 1: ram_constants
Info: Found design unit 2: controlunit-structual
Info: Found entity 1: controlunit
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
Info: Found entity 1: Block1
Info: Elaborating entity "controlunit" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at controlunit.vhd(40): object "decode_ir" declared but not used
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus51/libraries/megafunctions/LPM_ROM.tdf
Info: Found entity 1: lpm_rom
Info: Elaborating entity "LPM_ROM" for hierarchy "LPM_ROM:U5"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus51/libraries/megafunctions/altrom.tdf
Info: Found entity 1: altrom
Info: Elaborating entity "altrom" for hierarchy "LPM_ROM:U5|altrom:srom"
Info: Issued messages during elaboration of megafunction "LPM_ROM:U5|altrom:srom", which is child of megafunction "LPM_ROM:U5"
Info: Instantiated megafunction "LPM_ROM:U5" with the following parameter:
Info: Parameter "LPM_WIDTH" = "8"
Info: Parameter "LPM_WIDTHAD" = "8"
Info: Parameter "LPM_NUMWORDS" = "0"
Info: Parameter "LPM_ADDRESS_CONTROL" = "REGISTERED"
Info: Parameter "LPM_OUTDATA" = "UNREGISTERED"
Info: Parameter "LPM_FILE" = "controlunit.mif"
Info: Parameter "LPM_TYPE" = "LPM_ROM"
Info: Parameter "INTENDED_DEVICE_FAMILY" = "UNUSED"
Info: Parameter "LPM_HINT" = "UNUSED"
Info: Parameter " constraint(address)" = "7 downto 0"
Info: Parameter " constraint(q)" = "7 downto 0"
Warning: Assertion warning: altrom does not support Stratix device family -- attempting best-case memory conversions, but power-up states will be different for Stratix devices
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus51/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "LPM_ROM:U5|altrom:srom|altsyncram:rom_block"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vcp.tdf
Info: Found entity 1: altsyncram_vcp
Info: Elaborating entity "altsyncram_vcp" for hierarchy "LPM_ROM:U5|altrom:srom|altsyncram:rom_block|altsyncram_vcp:auto_generated"
Info: Power-up level of register "we" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "we" with stuck data_in port to stuck value VCC
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
Warning: Converting TRI node "lpm_rom:U5|otri[7]" that feeds logic to a wire
Warning: Converting TRI node "lpm_rom:U5|otri[6]" that feeds logic to a wire
Warning: Converting TRI node "lpm_rom:U5|otri[5]" that feeds logic to a wire
Warning: Converting TRI node "lpm_rom:U5|otri[4]" that feeds logic to a wire
Warning: Converting TRI node "lpm_rom:U5|otri[3]" that feeds logic to a wire
Warning: Converting TRI node "lpm_rom:U5|otri[2]" that feeds logic to a wire
Warning: Converting TRI node "lpm_rom:U5|otri[1]" that feeds logic to a wire
Warning: Converting TRI node "lpm_rom:U5|otri[0]" that feeds logic to a wire
Info: Duplicate registers merged to single register
Info: Duplicate register "temp[5]" merged to single register "temp[7]"
Info: Duplicate register "temp[6]" merged to single register "temp[7]"
Info: Duplicate register "temp[4]" merged to single register "temp[7]"
Info: Duplicate register "temp[0]" merged to single register "temp[3]"
Info: Duplicate register "temp[2]" merged to single register "temp[3]"
Info: Duplicate register "temp[1]" merged to single register "temp[3]"
Warning: Reduced register "temp[7]" with stuck data_in port to stuck value GND
Info: Power-up level of register "temp[3]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "temp[3]" with stuck data_in port to stuck value VCC
Warning: Design contains 6 input pin(s) that do not drive logic
Warning: No output dependent on input pin "flag[0]"
Warning: No output dependent on input pin "flag[1]"
Warning: No output dependent on input pin "flag[2]"
Warning: No output dependent on input pin "flag[3]"
Warning: No output dependent on input pin "flag[5]"
Warning: No output dependent on input pin "flag[6]"
Info: Implemented 116 device resources after synthesis - the final resource count might be different
Info: Implemented 17 input pins
Info: Implemented 8 output pins
Info: Implemented 83 logic cells
Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings
Info: Processing ended: Fri Apr 18 08:50:40 2008
Info: Elapsed time: 00:00:03
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