i2c_master_top.map.eqn

verilog在cpld上实现i2c主从设备通讯功能

--B1L49 is i2c_master_byte_ctrl:byte_controller|ld~90
--operation mode is normal

B1L49 = C1_cmd_ack & B1_c_state.ST_START;


--B1_c_state.ST_WRITE is i2c_master_byte_ctrl:byte_controller|c_state.ST_WRITE
--operation mode is normal

B1_c_state.ST_WRITE_lut_out = B1L5 & (B1L19 # B1_c_state.ST_WRITE & !B1L15);
B1_c_state.ST_WRITE = DFFEAS(B1_c_state.ST_WRITE_lut_out, wb_clk_i, arst_i, , , , , , );


--B1_dcnt[2] is i2c_master_byte_ctrl:byte_controller|dcnt[2]
--operation mode is normal

B1_dcnt[2]_lut_out = !wb_rst_i & (B1_ld # B1_dcnt[2] $ B1L50);
B1_dcnt[2] = DFFEAS(B1_dcnt[2]_lut_out, wb_clk_i, arst_i, , B1L44, , , , );


--B1_dcnt[1] is i2c_master_byte_ctrl:byte_controller|dcnt[1]
--operation mode is normal

B1_dcnt[1]_lut_out = !wb_rst_i & (B1_ld # B1_dcnt[1] $ !B1_dcnt[0]);
B1_dcnt[1] = DFFEAS(B1_dcnt[1]_lut_out, wb_clk_i, arst_i, , B1L44, , , , );


--B1_dcnt[0] is i2c_master_byte_ctrl:byte_controller|dcnt[0]
--operation mode is normal

B1_dcnt[0]_lut_out = !wb_rst_i & (B1_ld # !B1_dcnt[0]);
B1_dcnt[0] = DFFEAS(B1_dcnt[0]_lut_out, wb_clk_i, arst_i, , B1L44, , , , );


--B1L52 is i2c_master_byte_ctrl:byte_controller|shift~98
--operation mode is normal

B1L52 = B1_c_state.ST_WRITE & (B1_dcnt[2] # B1_dcnt[1] # B1_dcnt[0]);


--C1_dSDA is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|dSDA
--operation mode is normal

C1_dSDA_lut_out = !wb_rst_i & (C1_sSDA);
C1_dSDA = DFFEAS(C1_dSDA_lut_out, wb_clk_i, arst_i, , , , , , );


--B1L32 is i2c_master_byte_ctrl:byte_controller|core_cmd~1548
--operation mode is normal

B1L32 = B1_c_state.ST_IDLE & (B1_core_cmd[0]) # !B1_c_state.ST_IDLE & (B1L47 & cr[7] # !B1L47 & (B1_core_cmd[0]));


--B1L28 is i2c_master_byte_ctrl:byte_controller|core_cmd[3]~1550
--operation mode is normal

B1L28 = !B1_c_state.ST_READ & !B1_c_state.ST_WRITE;


--B1L29 is i2c_master_byte_ctrl:byte_controller|core_cmd[3]~1551
--operation mode is normal

B1L29 = B1_c_state.ST_READ # B1_c_state.ST_START & (!B1_c_state.ST_WRITE);


--B1L33 is i2c_master_byte_ctrl:byte_controller|core_cmd~1552
--operation mode is normal

B1L33 = cr[5] & B1L28 & (B1L29 # !cr[7]);


--B1L50 is i2c_master_byte_ctrl:byte_controller|reduce_or~24
--operation mode is normal

B1L50 = !B1_dcnt[1] & !B1_dcnt[0];


--B1L30 is i2c_master_byte_ctrl:byte_controller|core_cmd[3]~1553
--operation mode is normal

B1L30 = !B1_c_state.ST_READ & !B1_c_state.ST_START & !B1_c_state.ST_WRITE;


--B1L34 is i2c_master_byte_ctrl:byte_controller|core_cmd~1555
--operation mode is normal

B1L34 = B1_c_state.ST_IDLE & (C1_cmd_ack) # !B1_c_state.ST_IDLE & B1L47 # !B1L5;


--B1L35 is i2c_master_byte_ctrl:byte_controller|core_cmd~1556
--operation mode is normal

B1L35 = B1L29 $ (!B1L28 & B1L50 & !B1_dcnt[2]);


--B1L36 is i2c_master_byte_ctrl:byte_controller|core_cmd~1557
--operation mode is normal

B1L36 = cr[5] & (B1L35) # !cr[5] & cr[4] & !cr[7] & !B1L35;


--B1_c_state.ST_STOP is i2c_master_byte_ctrl:byte_controller|c_state.ST_STOP
--operation mode is normal

B1_c_state.ST_STOP_lut_out = B1L5 & (B1_c_state.ST_STOP & !C1_cmd_ack # !B1L13);
B1_c_state.ST_STOP = DFFEAS(B1_c_state.ST_STOP_lut_out, wb_clk_i, arst_i, , , , , , );


--B1L37 is i2c_master_byte_ctrl:byte_controller|core_cmd~1559
--operation mode is normal

B1L37 = B1_c_state.ST_ACK # B1_c_state.ST_STOP # !B1L30;


--B1L38 is i2c_master_byte_ctrl:byte_controller|core_cmd~1560
--operation mode is normal

B1L38 = B1L37 & (!B1_c_state.ST_IDLE & !B1L47 # !C1_cmd_ack) # !B1L37 & !B1_c_state.ST_IDLE & !B1L47;


--B1L12 is i2c_master_byte_ctrl:byte_controller|c_state~1082
--operation mode is normal

B1L12 = cr[6] & B1_c_state.ST_ACK & C1_cmd_ack;


--B1L13 is i2c_master_byte_ctrl:byte_controller|c_state~1083
--operation mode is normal

B1L13 = !B1L12 & (B1_c_state.ST_IDLE # !B1L22 # !B1L47);


--C1_cmd_stop is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cmd_stop
--operation mode is normal

C1_cmd_stop_lut_out = !B1_core_cmd[3] & !B1_core_cmd[2] & B1_core_cmd[1] & !B1_core_cmd[0];
C1_cmd_stop = DFFEAS(C1_cmd_stop_lut_out, wb_clk_i, arst_i, , , , , wb_rst_i, );


--C1_c_state.start_c is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.start_c
--operation mode is normal

C1_c_state.start_c_lut_out = B1L5 & (C1_clk_en & C1_c_state.start_c # !C1_clk_en & (C1_c_state.start_b));
C1_c_state.start_c = DFFEAS(C1_c_state.start_c_lut_out, wb_clk_i, arst_i, , , , , , );


--C1L75 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[15]~709
--operation mode is normal

C1L75 = wb_rst_i # !C1L6 # !C1_sSCL # !C1_dscl_oen;


--B1L14 is i2c_master_byte_ctrl:byte_controller|c_state~1084
--operation mode is normal

B1L14 = B1_c_state.ST_ACK & (!C1_cmd_ack);


--B1L15 is i2c_master_byte_ctrl:byte_controller|c_state~1085
--operation mode is normal

B1L15 = C1_cmd_ack & !B1_dcnt[2] & !B1_dcnt[1] & !B1_dcnt[0];


--B1L16 is i2c_master_byte_ctrl:byte_controller|c_state~1087
--operation mode is normal

B1L16 = !cr[7] & !B1_cmd_ack & !B1_c_state.ST_IDLE;


--C1_c_state.stop_b is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.stop_b
--operation mode is normal

C1_c_state.stop_b_lut_out = B1L5 & (C1_clk_en & C1_c_state.stop_b # !C1_clk_en & (C1_c_state.stop_a));
C1_c_state.stop_b = DFFEAS(C1_c_state.stop_b_lut_out, wb_clk_i, arst_i, , , , , , );


--B1L17 is i2c_master_byte_ctrl:byte_controller|c_state~1089
--operation mode is normal

B1L17 = C1_cmd_ack & (B1_c_state.ST_STOP # B1_c_state.ST_ACK & !cr[6]);


--B1L18 is i2c_master_byte_ctrl:byte_controller|c_state~1091
--operation mode is normal

B1L18 = B1_c_state.ST_IDLE & B1_c_state.ST_START & (!C1_cmd_ack);


--B1L19 is i2c_master_byte_ctrl:byte_controller|c_state~1093
--operation mode is normal

B1L19 = !cr[5] & (B1L49 # cr[4] & B1L16);


--B1L39 is i2c_master_byte_ctrl:byte_controller|core_cmd~1562
--operation mode is normal

B1L39 = B1L29 $ (!B1_dcnt[1] & !B1_dcnt[0] & !B1_dcnt[2]);


--B1L31 is i2c_master_byte_ctrl:byte_controller|core_cmd[3]~1563
--operation mode is normal

B1L31 = C1_al # wb_rst_i # B1_c_state.ST_IDLE & B1L30;


--B1L20 is i2c_master_byte_ctrl:byte_controller|c_state~1096
--operation mode is normal

B1L20 = cr[5] & (B1L16 # C1_cmd_ack & B1_c_state.ST_START);


--wb_adr_i[0] is wb_adr_i[0]
--operation mode is input

wb_adr_i[0] = INPUT();


--wb_adr_i[2] is wb_adr_i[2]
--operation mode is input

wb_adr_i[2] = INPUT();


--wb_adr_i[1] is wb_adr_i[1]
--operation mode is input

wb_adr_i[1] = INPUT();


--wb_clk_i is wb_clk_i
--operation mode is input

wb_clk_i = INPUT();


--wb_stb_i is wb_stb_i
--operation mode is input

wb_stb_i = INPUT();


--wb_cyc_i is wb_cyc_i
--operation mode is input

wb_cyc_i = INPUT();


--arst_i is arst_i
--operation mode is input

arst_i = INPUT();


--wb_rst_i is wb_rst_i
--operation mode is input

wb_rst_i = INPUT();


--wb_dat_i[0] is wb_dat_i[0]
--operation mode is input

wb_dat_i[0] = INPUT();


--wb_we_i is wb_we_i
--operation mode is input

wb_we_i = INPUT();


--wb_dat_i[1] is wb_dat_i[1]
--operation mode is input

wb_dat_i[1] = INPUT();


--wb_dat_i[2] is wb_dat_i[2]
--operation mode is input

wb_dat_i[2] = INPUT();


--wb_dat_i[3] is wb_dat_i[3]
--operation mode is input

wb_dat_i[3] = INPUT();


--wb_dat_i[4] is wb_dat_i[4]
--operation mode is input

wb_dat_i[4] = INPUT();


--wb_dat_i[5] is wb_dat_i[5]
--operation mode is input

wb_dat_i[5] = INPUT();


--wb_dat_i[6] is wb_dat_i[6]
--operation mode is input

wb_dat_i[6] = INPUT();


--wb_dat_i[7] is wb_dat_i[7]
--operation mode is input

wb_dat_i[7] = INPUT();


--sda_pad_i is sda_pad_i
--operation mode is input

sda_pad_i = INPUT();


--scl_pad_i is scl_pad_i
--operation mode is input

scl_pad_i = INPUT();


--wb_dat_o[0] is wb_dat_o[0]
--operation mode is output

wb_dat_o[0] = OUTPUT(A1L152Q);


--wb_dat_o[1] is wb_dat_o[1]
--operation mode is output

wb_dat_o[1] = OUTPUT(A1L154Q);


--wb_dat_o[2] is wb_dat_o[2]
--operation mode is output

wb_dat_o[2] = OUTPUT(A1L156Q);


--wb_dat_o[3] is wb_dat_o[3]
--operation mode is output

wb_dat_o[3] = OUTPUT(A1L158Q);


--wb_dat_o[4] is wb_dat_o[4]
--operation mode is output

wb_dat_o[4] = OUTPUT(A1L161Q);


--wb_dat_o[5] is wb_dat_o[5]
--operation mode is output

wb_dat_o[5] = OUTPUT(A1L163Q);


--wb_dat_o[6] is wb_dat_o[6]
--operation mode is output

wb_dat_o[6] = OUTPUT(A1L165Q);


--wb_dat_o[7] is wb_dat_o[7]
--operation mode is output

wb_dat_o[7] = OUTPUT(A1L167Q);


--wb_ack_o is wb_ack_o
--operation mode is output

wb_ack_o = OUTPUT(A1L132Q);


--wb_inta_o is wb_inta_o
--operation mode is output

wb_inta_o = OUTPUT(A1L169Q);


--scl_pad_o is scl_pad_o
--operation mode is output

scl_pad_o = OUTPUT(GND);


--scl_padoen_o is scl_padoen_o
--operation mode is output

scl_padoen_o = OUTPUT(!C1_scl_oen);


--sda_pad_o is sda_pad_o
--operation mode is output

sda_pad_o = OUTPUT(GND);


--sda_padoen_o is sda_padoen_o
--operation mode is output

sda_padoen_o = OUTPUT(!C1_sda_oen);


--A1L67 is prer[0]~292
--operation mode is normal

A1L67 = !prer[0];


--A1L89 is prer[10]~293
--operation mode is normal

A1L89 = !prer[10];


--A1L91 is prer[11]~294
--operation mode is normal

A1L91 = !prer[11];


--A1L93 is prer[12]~295
--operation mode is normal

A1L93 = !prer[12];


--A1L95 is prer[13]~296
--operation mode is normal

A1L95 = !prer[13];


--A1L97 is prer[14]~297
--operation mode is normal

A1L97 = !prer[14];


--A1L99 is prer[15]~298
--operation mode is normal

A1L99 = !prer[15];


--A1L69 is prer[1]~299
--operation mode is normal

A1L69 = !prer[1];


--A1L71 is prer[2]~300
--operation mode is normal

A1L71 = !prer[2];


--A1L73 is prer[3]~301
--operation mode is normal

A1L73 = !prer[3];


--A1L76 is prer[4]~302
--operation mode is normal

A1L76 = !prer[4];


--A1L78 is prer[5]~303
--operation mode is normal

A1L78 = !prer[5];


--A1L80 is prer[6]~304
--operation mode is normal

A1L80 = !prer[6];


--A1L82 is prer[7]~305
--operation mode is normal

A1L82 = !prer[7];


--A1L84 is prer[8]~306
--operation mode is normal

A1L84 = !prer[8];


--A1L87 is prer[9]~307
--operation mode is normal

A1L87 = !prer[9];