i2c_master_top.map.eqn

verilog在cpld上实现i2c主从设备通讯功能

--operation mode is normal

C1_sto_condition_lut_out = !C1_sSDA & !C1_sSCL & (C1_dSDA);
C1_sto_condition = DFFEAS(C1_sto_condition_lut_out, wb_clk_i, arst_i, , , , , wb_rst_i, );


--C1_sta_condition is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sta_condition
--operation mode is normal

C1_sta_condition_lut_out = C1_sSDA & !C1_sSCL & (!C1_dSDA);
C1_sta_condition = DFFEAS(C1_sta_condition_lut_out, wb_clk_i, arst_i, , , , , wb_rst_i, );


--A1L62 is ctr~209
--operation mode is normal

A1L62 = wb_dat_i[6] & (!wb_rst_i);


--A1L106 is prer~274
--operation mode is normal

A1L106 = wb_rst_i # wb_dat_i[6];


--A1L63 is ctr~210
--operation mode is normal

A1L63 = wb_dat_i[7] & (!wb_rst_i);


--B1_ack_out is i2c_master_byte_ctrl:byte_controller|ack_out
--operation mode is normal

B1_ack_out_lut_out = B1L5 & (B1L2 & C1_dout # !B1L2 & (B1_ack_out));
B1_ack_out = DFFEAS(B1_ack_out_lut_out, wb_clk_i, arst_i, , , , , , );


--A1L107 is prer~275
--operation mode is normal

A1L107 = wb_rst_i # wb_dat_i[7];


--B1_core_cmd[0] is i2c_master_byte_ctrl:byte_controller|core_cmd[0]
--operation mode is normal

B1_core_cmd[0]_lut_out = B1L5 & B1L32 & (!B1_c_state.ST_IDLE # !C1_cmd_ack);
B1_core_cmd[0] = DFFEAS(B1_core_cmd[0]_lut_out, wb_clk_i, arst_i, , , , , , );


--B1_core_cmd[3] is i2c_master_byte_ctrl:byte_controller|core_cmd[3]
--operation mode is normal

B1_core_cmd[3]_lut_out = !B1L31 & (B1L33 # B1L39 & !B1L28);
B1_core_cmd[3] = DFFEAS(B1_core_cmd[3]_lut_out, wb_clk_i, arst_i, , B1L34, , , , );


--B1_core_cmd[2] is i2c_master_byte_ctrl:byte_controller|core_cmd[2]
--operation mode is normal

B1_core_cmd[2]_lut_out = !B1L31 & (B1L35 $ (B1L36 # !B1L28));
B1_core_cmd[2] = DFFEAS(B1_core_cmd[2]_lut_out, wb_clk_i, arst_i, , B1L34, , , , );


--B1_core_cmd[1] is i2c_master_byte_ctrl:byte_controller|core_cmd[1]
--operation mode is normal

B1_core_cmd[1]_lut_out = B1L5 & (B1_core_cmd[1] & B1L38 # !B1L13);
B1_core_cmd[1] = DFFEAS(B1_core_cmd[1]_lut_out, wb_clk_i, arst_i, , , , , , );


--C1L1 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|Decoder~128
--operation mode is normal

C1L1 = B1_core_cmd[0] & !B1_core_cmd[3] & !B1_core_cmd[2] & !B1_core_cmd[1];


--C1L29 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state~1596
--operation mode is normal

C1L29 = C1_clk_en & C1_c_state.start_a # !C1_clk_en & (C1L1 & !C1_c_state.idle);


--C1L30 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state~1597
--operation mode is normal

C1L30 = B1_core_cmd[3] & (B1_core_cmd[2] # B1_core_cmd[1] # B1_core_cmd[0]) # !B1_core_cmd[3] & (B1_core_cmd[2] & (B1_core_cmd[1] # B1_core_cmd[0]) # !B1_core_cmd[2] & (B1_core_cmd[1] $ !B1_core_cmd[0]));


--C1L31 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state~1598
--operation mode is normal

C1L31 = !C1_c_state.idle & (C1_clk_en # C1L30);


--C1L81 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|reduce_or~31
--operation mode is normal

C1L81 = C1_c_state.rd_d # C1_c_state.start_e # C1_c_state.wr_d # C1_c_state.stop_d;


--C1_sda_chk is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_chk
--operation mode is normal

C1_sda_chk_lut_out = !C1_al & !wb_rst_i & (C1_c_state.wr_b # C1_c_state.wr_c);
C1_sda_chk = DFFEAS(C1_sda_chk_lut_out, wb_clk_i, arst_i, , A1L108, , , , );


--C1_sSDA is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sSDA
--operation mode is normal

C1_sSDA_lut_out = !wb_rst_i & !sda_pad_i;
C1_sSDA = DFFEAS(C1_sSDA_lut_out, wb_clk_i, arst_i, , , , , , );


--C1L7 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|al~49
--operation mode is normal

C1L7 = C1_sda_chk & C1_sSDA & (!C1_sda_oen);


--C1_dcmd_stop is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|dcmd_stop
--operation mode is normal

C1_dcmd_stop_lut_out = C1_cmd_stop & (!wb_rst_i);
C1_dcmd_stop = DFFEAS(C1_dcmd_stop_lut_out, wb_clk_i, arst_i, , , , , , );


--C1L2 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|Decoder~129
--operation mode is normal

C1L2 = B1_core_cmd[3] & !B1_core_cmd[2] & !B1_core_cmd[1] & !B1_core_cmd[0];


--C1L32 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state~1600
--operation mode is normal

C1L32 = C1_clk_en & C1_c_state.rd_a # !C1_clk_en & (C1L2 & !C1_c_state.idle);


--C1_c_state.start_d is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.start_d
--operation mode is normal

C1_c_state.start_d_lut_out = B1L5 & (C1_clk_en & C1_c_state.start_d # !C1_clk_en & (C1_c_state.start_c));
C1_c_state.start_d = DFFEAS(C1_c_state.start_d_lut_out, wb_clk_i, arst_i, , , , , , );


--C1L3 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|Decoder~130
--operation mode is normal

C1L3 = B1_core_cmd[2] & !B1_core_cmd[3] & !B1_core_cmd[1] & !B1_core_cmd[0];


--C1L33 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state~1604
--operation mode is normal

C1L33 = C1_clk_en & C1_c_state.wr_a # !C1_clk_en & (C1L3 & !C1_c_state.idle);


--C1L4 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|Decoder~131
--operation mode is normal

C1L4 = B1_core_cmd[1] & !B1_core_cmd[3] & !B1_core_cmd[2] & !B1_core_cmd[0];


--C1L34 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state~1605
--operation mode is normal

C1L34 = C1_clk_en & C1_c_state.stop_a # !C1_clk_en & (C1L4 & !C1_c_state.idle);


--C1_cnt[0] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[0]
--operation mode is arithmetic

C1_cnt[0]_lut_out = !C1_cnt[0];
C1_cnt[0] = DFFEAS(C1_cnt[0]_lut_out, wb_clk_i, arst_i, , C1L75, A1L67, , wb_rst_i, C1L6);

--C1L40 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[0]~641
--operation mode is arithmetic

C1L40 = CARRY(C1_cnt[0]);


--C1_cnt[1] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[1]
--operation mode is arithmetic

C1_cnt[1]_carry_eqn = C1L40;
C1_cnt[1]_lut_out = C1_cnt[1] $ (!C1_cnt[1]_carry_eqn);
C1_cnt[1] = DFFEAS(C1_cnt[1]_lut_out, wb_clk_i, arst_i, , C1L75, A1L69, , wb_rst_i, C1L6);

--C1L42 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[1]~645
--operation mode is arithmetic

C1L42 = CARRY(!C1_cnt[1] & (!C1L40));


--C1L70 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[15]~648
--operation mode is normal

C1L70 = !C1_cnt[0] & !C1_cnt[1];


--C1_cnt[4] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[4]
--operation mode is arithmetic

C1_cnt[4]_carry_eqn = C1L46;
C1_cnt[4]_lut_out = C1_cnt[4] $ (C1_cnt[4]_carry_eqn);
C1_cnt[4] = DFFEAS(C1_cnt[4]_lut_out, wb_clk_i, arst_i, , C1L75, A1L76, , wb_rst_i, C1L6);

--C1L48 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[4]~650
--operation mode is arithmetic

C1L48 = CARRY(C1_cnt[4] # !C1L46);


--C1_cnt[5] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[5]
--operation mode is arithmetic

C1_cnt[5]_carry_eqn = C1L48;
C1_cnt[5]_lut_out = C1_cnt[5] $ (!C1_cnt[5]_carry_eqn);
C1_cnt[5] = DFFEAS(C1_cnt[5]_lut_out, wb_clk_i, arst_i, , C1L75, A1L78, , wb_rst_i, C1L6);

--C1L50 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[5]~654
--operation mode is arithmetic

C1L50 = CARRY(!C1_cnt[5] & (!C1L48));


--C1_cnt[6] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[6]
--operation mode is arithmetic

C1_cnt[6]_carry_eqn = C1L50;
C1_cnt[6]_lut_out = C1_cnt[6] $ (C1_cnt[6]_carry_eqn);
C1_cnt[6] = DFFEAS(C1_cnt[6]_lut_out, wb_clk_i, arst_i, , C1L75, A1L80, , wb_rst_i, C1L6);

--C1L52 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[6]~658
--operation mode is arithmetic

C1L52 = CARRY(C1_cnt[6] # !C1L50);


--C1_cnt[7] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[7]
--operation mode is arithmetic

C1_cnt[7]_carry_eqn = C1L52;
C1_cnt[7]_lut_out = C1_cnt[7] $ (!C1_cnt[7]_carry_eqn);
C1_cnt[7] = DFFEAS(C1_cnt[7]_lut_out, wb_clk_i, arst_i, , C1L75, A1L82, , wb_rst_i, C1L6);

--C1L54 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[7]~662
--operation mode is arithmetic

C1L54 = CARRY(!C1_cnt[7] & (!C1L52));


--C1L71 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[15]~665
--operation mode is normal

C1L71 = !C1_cnt[4] & !C1_cnt[5] & !C1_cnt[6] & !C1_cnt[7];


--C1_cnt[2] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[2]
--operation mode is arithmetic

C1_cnt[2]_carry_eqn = C1L42;
C1_cnt[2]_lut_out = C1_cnt[2] $ (C1_cnt[2]_carry_eqn);
C1_cnt[2] = DFFEAS(C1_cnt[2]_lut_out, wb_clk_i, arst_i, , C1L75, A1L71, , wb_rst_i, C1L6);

--C1L44 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[2]~667
--operation mode is arithmetic

C1L44 = CARRY(C1_cnt[2] # !C1L42);


--C1_cnt[3] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[3]
--operation mode is arithmetic

C1_cnt[3]_carry_eqn = C1L44;
C1_cnt[3]_lut_out = C1_cnt[3] $ (!C1_cnt[3]_carry_eqn);
C1_cnt[3] = DFFEAS(C1_cnt[3]_lut_out, wb_clk_i, arst_i, , C1L75, A1L73, , wb_rst_i, C1L6);

--C1L46 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[3]~671
--operation mode is arithmetic

C1L46 = CARRY(!C1_cnt[3] & (!C1L44));


--C1L72 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[15]~674
--operation mode is normal

C1L72 = C1L70 & C1L71 & !C1_cnt[2] & !C1_cnt[3];


--C1_cnt[8] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[8]
--operation mode is arithmetic

C1_cnt[8]_carry_eqn = C1L54;
C1_cnt[8]_lut_out = C1_cnt[8] $ (C1_cnt[8]_carry_eqn);
C1_cnt[8] = DFFEAS(C1_cnt[8]_lut_out, wb_clk_i, arst_i, , C1L75, A1L84, , wb_rst_i, C1L6);

--C1L56 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[8]~676
--operation mode is arithmetic

C1L56 = CARRY(C1_cnt[8] # !C1L54);


--C1_cnt[9] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[9]
--operation mode is arithmetic

C1_cnt[9]_carry_eqn = C1L56;
C1_cnt[9]_lut_out = C1_cnt[9] $ (!C1_cnt[9]_carry_eqn);
C1_cnt[9] = DFFEAS(C1_cnt[9]_lut_out, wb_clk_i, arst_i, , C1L75, A1L87, , wb_rst_i, C1L6);

--C1L58 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[9]~680
--operation mode is arithmetic

C1L58 = CARRY(!C1_cnt[9] & (!C1L56));


--C1_cnt[10] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[10]
--operation mode is arithmetic

C1_cnt[10]_carry_eqn = C1L58;
C1_cnt[10]_lut_out = C1_cnt[10] $ (C1_cnt[10]_carry_eqn);
C1_cnt[10] = DFFEAS(C1_cnt[10]_lut_out, wb_clk_i, arst_i, , C1L75, A1L89, , wb_rst_i, C1L6);

--C1L60 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[10]~684
--operation mode is arithmetic

C1L60 = CARRY(C1_cnt[10] # !C1L58);


--C1_cnt[11] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[11]
--operation mode is arithmetic

C1_cnt[11]_carry_eqn = C1L60;
C1_cnt[11]_lut_out = C1_cnt[11] $ (!C1_cnt[11]_carry_eqn);
C1_cnt[11] = DFFEAS(C1_cnt[11]_lut_out, wb_clk_i, arst_i, , C1L75, A1L91, , wb_rst_i, C1L6);

--C1L62 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[11]~688
--operation mode is arithmetic

C1L62 = CARRY(!C1_cnt[11] & (!C1L60));


--C1L73 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[15]~691
--operation mode is normal

C1L73 = !C1_cnt[8] & !C1_cnt[9] & !C1_cnt[10] & !C1_cnt[11];


--C1_cnt[12] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[12]
--operation mode is arithmetic

C1_cnt[12]_carry_eqn = C1L62;
C1_cnt[12]_lut_out = C1_cnt[12] $ (C1_cnt[12]_carry_eqn);
C1_cnt[12] = DFFEAS(C1_cnt[12]_lut_out, wb_clk_i, arst_i, , C1L75, A1L93, , wb_rst_i, C1L6);

--C1L64 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[12]~693
--operation mode is arithmetic

C1L64 = CARRY(C1_cnt[12] # !C1L62);


--C1_cnt[13] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[13]
--operation mode is arithmetic

C1_cnt[13]_carry_eqn = C1L64;
C1_cnt[13]_lut_out = C1_cnt[13] $ (!C1_cnt[13]_carry_eqn);
C1_cnt[13] = DFFEAS(C1_cnt[13]_lut_out, wb_clk_i, arst_i, , C1L75, A1L95, , wb_rst_i, C1L6);

--C1L66 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[13]~697
--operation mode is arithmetic

C1L66 = CARRY(!C1_cnt[13] & (!C1L64));


--C1_cnt[14] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[14]
--operation mode is arithmetic

C1_cnt[14]_carry_eqn = C1L66;
C1_cnt[14]_lut_out = C1_cnt[14] $ (C1_cnt[14]_carry_eqn);
C1_cnt[14] = DFFEAS(C1_cnt[14]_lut_out, wb_clk_i, arst_i, , C1L75, A1L97, , wb_rst_i, C1L6);

--C1L68 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[14]~701
--operation mode is arithmetic

C1L68 = CARRY(C1_cnt[14] # !C1L66);


--C1_cnt[15] is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[15]
--operation mode is normal

C1_cnt[15]_carry_eqn = C1L68;
C1_cnt[15]_lut_out = C1_cnt[15] $ (!C1_cnt[15]_carry_eqn);
C1_cnt[15] = DFFEAS(C1_cnt[15]_lut_out, wb_clk_i, arst_i, , C1L75, A1L99, , wb_rst_i, C1L6);


--C1L74 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[15]~708
--operation mode is normal

C1L74 = !C1_cnt[12] & !C1_cnt[13] & !C1_cnt[14] & !C1_cnt[15];


--C1L6 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|always1~0
--operation mode is normal

C1L6 = C1L72 & C1L73 & C1L74 # !ctr[7];


--C1_dscl_oen is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|dscl_oen
--operation mode is normal

C1_dscl_oen_lut_out = !C1_scl_oen;
C1_dscl_oen = DFFEAS(C1_dscl_oen_lut_out, wb_clk_i, VCC, , , , , , );


--C1_sSCL is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sSCL
--operation mode is normal

C1_sSCL_lut_out = !wb_rst_i & !scl_pad_i;
C1_sSCL = DFFEAS(C1_sSCL_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_cmd_ack is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cmd_ack
--operation mode is normal

C1_cmd_ack_lut_out = !C1_al & !wb_rst_i & C1L81 & !C1_clk_en;
C1_cmd_ack = DFFEAS(C1_cmd_ack_lut_out, wb_clk_i, arst_i, , , , , , );


--B1_c_state.ST_ACK is i2c_master_byte_ctrl:byte_controller|c_state.ST_ACK
--operation mode is normal

B1_c_state.ST_ACK_lut_out = B1L5 & (B1L14 # B1L15 & !B1L28);
B1_c_state.ST_ACK = DFFEAS(B1_c_state.ST_ACK_lut_out, wb_clk_i, arst_i, , , , , , );


--B1_c_state.ST_READ is i2c_master_byte_ctrl:byte_controller|c_state.ST_READ
--operation mode is normal

B1_c_state.ST_READ_lut_out = B1L5 & (B1L20 # B1_c_state.ST_READ & !B1L15);
B1_c_state.ST_READ = DFFEAS(B1_c_state.ST_READ_lut_out, wb_clk_i, arst_i, , , , , , );


--B1L1 is i2c_master_byte_ctrl:byte_controller|Select~459
--operation mode is normal

B1L1 = C1_cmd_ack & (B1_c_state.ST_ACK # !B1_c_state.ST_READ) # !C1_cmd_ack & !B1_c_state.ST_ACK;


--B1L41 is i2c_master_byte_ctrl:byte_controller|core_txd~259
--operation mode is normal

B1L41 = B1L1 & (B1_sr[7] # B1_c_state.ST_ACK) # !B1L1 & cr[3];


--C1_c_state.stop_c is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.stop_c
--operation mode is normal

C1_c_state.stop_c_lut_out = B1L5 & (C1_clk_en & C1_c_state.stop_c # !C1_clk_en & (C1_c_state.stop_b));
C1_c_state.stop_c = DFFEAS(C1_c_state.stop_c_lut_out, wb_clk_i, arst_i, , , , , , );


--B1L2 is i2c_master_byte_ctrl:byte_controller|Select~460
--operation mode is normal

B1L2 = B1_c_state.ST_ACK & C1_cmd_ack;


--B1L47 is i2c_master_byte_ctrl:byte_controller|go~44
--operation mode is normal

B1L47 = !B1_cmd_ack & (cr[4] # cr[5] # cr[6]);


--B1_c_state.ST_IDLE is i2c_master_byte_ctrl:byte_controller|c_state.ST_IDLE
--operation mode is normal

B1_c_state.ST_IDLE_lut_out = !B1L17 & B1L5 & (B1_c_state.ST_IDLE # B1L47);
B1_c_state.ST_IDLE = DFFEAS(B1_c_state.ST_IDLE_lut_out, wb_clk_i, arst_i, , , , , , );


--B1L3 is i2c_master_byte_ctrl:byte_controller|Select~461
--operation mode is normal

B1L3 = B1L47 & (!B1_c_state.ST_IDLE);


--B1L22 is i2c_master_byte_ctrl:byte_controller|cmd_ack~55
--operation mode is normal

B1L22 = !cr[4] & !cr[5] & !cr[7];


--C1_dSCL is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|dSCL
--operation mode is normal

C1_dSCL_lut_out = C1_sSCL & (!wb_rst_i);
C1_dSCL = DFFEAS(C1_dSCL_lut_out, wb_clk_i, arst_i, , , , , , );


--B1_c_state.ST_START is i2c_master_byte_ctrl:byte_controller|c_state.ST_START
--operation mode is normal

B1_c_state.ST_START_lut_out = B1L5 & (B1L18 # cr[7] & B1L3);
B1_c_state.ST_START = DFFEAS(B1_c_state.ST_START_lut_out, wb_clk_i, arst_i, , , , , , );