i2c_master_top.map.eqn

verilog在cpld上实现i2c主从设备通讯功能

--operation mode is normal

A1L21 = A1L150 & (A1L20 & (B1_sr[5]) # !A1L20 & txr[5]) # !A1L150 & (A1L20);


--C1_busy is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|busy
--operation mode is normal

C1_busy_lut_out = !C1_sto_condition & (C1_busy # C1_sta_condition);
C1_busy = DFFEAS(C1_busy_lut_out, wb_clk_i, arst_i, , , , , wb_rst_i, );


--ctr[6] is ctr[6]
--operation mode is normal

ctr[6]_lut_out = A1L62;
ctr[6] = DFFEAS(ctr[6]_lut_out, wb_clk_i, arst_i, , A1L55, , , , );


--prer[6] is prer[6]
--operation mode is normal

prer[6]_lut_out = !A1L106;
prer[6] = DFFEAS(prer[6]_lut_out, wb_clk_i, arst_i, , A1L75, , , , );


--A1L22 is Select~942
--operation mode is normal

A1L22 = wb_adr_i[2] & (wb_adr_i[1]) # !wb_adr_i[2] & (wb_adr_i[1] & ctr[6] # !wb_adr_i[1] & (!prer[6]));


--cr[6] is cr[6]
--operation mode is normal

cr[6]_lut_out = wb_wacc & wb_dat_i[6] & (!wb_rst_i);
cr[6] = DFFEAS(cr[6]_lut_out, wb_clk_i, arst_i, , A1L44, , , , );


--A1L23 is Select~943
--operation mode is normal

A1L23 = wb_adr_i[2] & (A1L22 & (cr[6]) # !A1L22 & C1_busy) # !wb_adr_i[2] & (A1L22);


--txr[6] is txr[6]
--operation mode is normal

txr[6]_lut_out = A1L62;
txr[6] = DFFEAS(txr[6]_lut_out, wb_clk_i, arst_i, , A1L124, , , , );


--prer[14] is prer[14]
--operation mode is normal

prer[14]_lut_out = !A1L106;
prer[14] = DFFEAS(prer[14]_lut_out, wb_clk_i, arst_i, , A1L86, , , , );


--A1L24 is Select~944
--operation mode is normal

A1L24 = A1L151 & (A1L150 & txr[6] # !A1L150 & (!prer[14])) # !A1L151 & (A1L150);


--B1_sr[6] is i2c_master_byte_ctrl:byte_controller|sr[6]
--operation mode is normal

B1_sr[6]_lut_out = B1_ld & (txr[6]) # !B1_ld & B1_sr[5];
B1_sr[6] = DFFEAS(B1_sr[6]_lut_out, wb_clk_i, arst_i, , B1L44, , , wb_rst_i, );


--A1L25 is Select~945
--operation mode is normal

A1L25 = A1L151 & (A1L24) # !A1L151 & (A1L24 & (B1_sr[6]) # !A1L24 & A1L23);


--txr[7] is txr[7]
--operation mode is normal

txr[7]_lut_out = A1L63;
txr[7] = DFFEAS(txr[7]_lut_out, wb_clk_i, arst_i, , A1L124, , , , );


--rxack is rxack
--operation mode is normal

rxack_lut_out = B1_ack_out & (!wb_rst_i);
rxack = DFFEAS(rxack_lut_out, wb_clk_i, arst_i, , , , , , );


--ctr[7] is ctr[7]
--operation mode is normal

ctr[7]_lut_out = A1L63;
ctr[7] = DFFEAS(ctr[7]_lut_out, wb_clk_i, arst_i, , A1L55, , , , );


--prer[7] is prer[7]
--operation mode is normal

prer[7]_lut_out = !A1L107;
prer[7] = DFFEAS(prer[7]_lut_out, wb_clk_i, arst_i, , A1L75, , , , );


--A1L26 is Select~947
--operation mode is normal

A1L26 = wb_adr_i[2] & (wb_adr_i[1]) # !wb_adr_i[2] & (wb_adr_i[1] & ctr[7] # !wb_adr_i[1] & (!prer[7]));


--cr[7] is cr[7]
--operation mode is normal

cr[7]_lut_out = wb_wacc & wb_dat_i[7] & (!wb_rst_i);
cr[7] = DFFEAS(cr[7]_lut_out, wb_clk_i, arst_i, , A1L44, , , , );


--A1L27 is Select~948
--operation mode is normal

A1L27 = wb_adr_i[2] & (A1L26 & (cr[7]) # !A1L26 & rxack) # !wb_adr_i[2] & (A1L26);


--prer[15] is prer[15]
--operation mode is normal

prer[15]_lut_out = !A1L107;
prer[15] = DFFEAS(prer[15]_lut_out, wb_clk_i, arst_i, , A1L86, , , , );


--A1L28 is Select~949
--operation mode is normal

A1L28 = A1L150 & (!A1L151) # !A1L150 & (A1L151 & (!prer[15]) # !A1L151 & A1L27);


--B1_sr[7] is i2c_master_byte_ctrl:byte_controller|sr[7]
--operation mode is normal

B1_sr[7]_lut_out = B1_ld & (txr[7]) # !B1_ld & B1_sr[6];
B1_sr[7] = DFFEAS(B1_sr[7]_lut_out, wb_clk_i, arst_i, , B1L44, , , wb_rst_i, );


--A1L29 is Select~950
--operation mode is normal

A1L29 = A1L150 & (A1L28 & (B1_sr[7]) # !A1L28 & txr[7]) # !A1L150 & (A1L28);


--C1_c_state.start_a is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.start_a
--operation mode is normal

C1_c_state.start_a_lut_out = !C1_al & !wb_rst_i & C1L29;
C1_c_state.start_a = DFFEAS(C1_c_state.start_a_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_c_state.idle is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.idle
--operation mode is normal

C1_c_state.idle_lut_out = !C1L31 & B1L5 & (C1_clk_en # !C1L81);
C1_c_state.idle = DFFEAS(C1_c_state.idle_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_al is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|al
--operation mode is normal

C1_al_lut_out = C1L7 # C1_sto_condition & (!C1_dcmd_stop);
C1_al = DFFEAS(C1_al_lut_out, wb_clk_i, arst_i, , , , , wb_rst_i, );


--B1L5 is i2c_master_byte_ctrl:byte_controller|always2~37
--operation mode is normal

B1L5 = !C1_al & !wb_rst_i;


--A1L109 is rtl~97
--operation mode is normal

A1L109 = !C1_scl_oen & (C1_c_state.start_a # !C1_c_state.idle) # !B1L5;


--C1_c_state.rd_a is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.rd_a
--operation mode is normal

C1_c_state.rd_a_lut_out = !C1_al & !wb_rst_i & C1L32;
C1_c_state.rd_a = DFFEAS(C1_c_state.rd_a_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_c_state.rd_d is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.rd_d
--operation mode is normal

C1_c_state.rd_d_lut_out = B1L5 & (C1_clk_en & C1_c_state.rd_d # !C1_clk_en & (C1_c_state.rd_c));
C1_c_state.rd_d = DFFEAS(C1_c_state.rd_d_lut_out, wb_clk_i, arst_i, , , , , , );


--C1L10 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.idle~57
--operation mode is normal

C1L10 = !C1_c_state.start_a & !C1_c_state.rd_a & !C1_c_state.rd_d;


--C1_c_state.start_e is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.start_e
--operation mode is normal

C1_c_state.start_e_lut_out = B1L5 & (C1_clk_en & C1_c_state.start_e # !C1_clk_en & (C1_c_state.start_d));
C1_c_state.start_e = DFFEAS(C1_c_state.start_e_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_c_state.wr_d is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.wr_d
--operation mode is normal

C1_c_state.wr_d_lut_out = B1L5 & (C1_clk_en & C1_c_state.wr_d # !C1_clk_en & (C1_c_state.wr_c));
C1_c_state.wr_d = DFFEAS(C1_c_state.wr_d_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_c_state.wr_a is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.wr_a
--operation mode is normal

C1_c_state.wr_a_lut_out = !C1_al & !wb_rst_i & C1L33;
C1_c_state.wr_a = DFFEAS(C1_c_state.wr_a_lut_out, wb_clk_i, arst_i, , , , , , );


--C1L11 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.idle~58
--operation mode is normal

C1L11 = C1_c_state.idle & !C1_c_state.start_e & !C1_c_state.wr_d & !C1_c_state.wr_a;


--C1_c_state.stop_a is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.stop_a
--operation mode is normal

C1_c_state.stop_a_lut_out = !C1_al & !wb_rst_i & C1L34;
C1_c_state.stop_a = DFFEAS(C1_c_state.stop_a_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_clk_en is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|clk_en
--operation mode is normal

C1_clk_en_lut_out = !wb_rst_i & (C1_dscl_oen & C1_sSCL # !C1L6);
C1_clk_en = DFFEAS(C1_clk_en_lut_out, wb_clk_i, arst_i, , , , , , );


--A1L108 is rtl~2
--operation mode is normal

A1L108 = C1_al # wb_rst_i # !C1_clk_en;


--C1L87 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_oen~205
--operation mode is normal

C1L87 = !C1_sda_oen & (C1_clk_en # !C1_c_state.idle) # !B1L5;


--B1_core_txd is i2c_master_byte_ctrl:byte_controller|core_txd
--operation mode is normal

B1_core_txd_lut_out = !C1_al & !wb_rst_i & B1L41;
B1_core_txd = DFFEAS(B1_core_txd_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_c_state.wr_b is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.wr_b
--operation mode is normal

C1_c_state.wr_b_lut_out = B1L5 & (C1_clk_en & C1_c_state.wr_b # !C1_clk_en & (C1_c_state.wr_a));
C1_c_state.wr_b = DFFEAS(C1_c_state.wr_b_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_c_state.wr_c is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.wr_c
--operation mode is normal

C1_c_state.wr_c_lut_out = B1L5 & (C1_clk_en & C1_c_state.wr_c # !C1_clk_en & (C1_c_state.wr_b));
C1_c_state.wr_c = DFFEAS(C1_c_state.wr_c_lut_out, wb_clk_i, arst_i, , , , , , );


--A1L110 is rtl~99
--operation mode is normal

A1L110 = !C1_c_state.wr_b & !C1_c_state.wr_c;


--C1L88 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_oen~206
--operation mode is normal

C1L88 = B1_core_txd & (C1_c_state.wr_d # C1_c_state.wr_a # !A1L110);


--C1_c_state.start_b is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.start_b
--operation mode is normal

C1_c_state.start_b_lut_out = B1L5 & (C1_clk_en & C1_c_state.start_b # !C1_clk_en & (C1_c_state.start_a));
C1_c_state.start_b = DFFEAS(C1_c_state.start_b_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_c_state.stop_d is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.stop_d
--operation mode is normal

C1_c_state.stop_d_lut_out = B1L5 & (C1_clk_en & C1_c_state.stop_d # !C1_clk_en & (C1_c_state.stop_c));
C1_c_state.stop_d = DFFEAS(C1_c_state.stop_d_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_c_state.rd_b is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.rd_b
--operation mode is normal

C1_c_state.rd_b_lut_out = B1L5 & (C1_clk_en & C1_c_state.rd_b # !C1_clk_en & (C1_c_state.rd_a));
C1_c_state.rd_b = DFFEAS(C1_c_state.rd_b_lut_out, wb_clk_i, arst_i, , , , , , );


--C1_c_state.rd_c is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.rd_c
--operation mode is normal

C1_c_state.rd_c_lut_out = B1L5 & (C1_clk_en & C1_c_state.rd_c # !C1_clk_en & (C1_c_state.rd_b));
C1_c_state.rd_c = DFFEAS(C1_c_state.rd_c_lut_out, wb_clk_i, arst_i, , , , , , );


--C1L89 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_oen~207
--operation mode is normal

C1L89 = C1_c_state.rd_b # C1_c_state.rd_c;


--C1L90 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_oen~208
--operation mode is normal

C1L90 = C1_c_state.start_b # C1_c_state.stop_d # C1L89 # !C1L10;


--A1L56 is ctr~202
--operation mode is normal

A1L56 = wb_dat_i[0] & (!wb_rst_i);


--A1L123 is txr[2]~133
--operation mode is normal

A1L123 = wb_stb_i & wb_cyc_i & wb_we_i & !wb_adr_i[2];


--A1L124 is txr[2]~134
--operation mode is normal

A1L124 = wb_rst_i # wb_adr_i[0] & wb_adr_i[1] & A1L123;


--A1L55 is ctr[7]~203
--operation mode is normal

A1L55 = wb_rst_i # !wb_adr_i[0] & wb_adr_i[1] & A1L123;


--B1_cmd_ack is i2c_master_byte_ctrl:byte_controller|cmd_ack
--operation mode is normal

B1_cmd_ack_lut_out = B1L5 & (B1L2 # B1L3 & B1L22);
B1_cmd_ack = DFFEAS(B1_cmd_ack_lut_out, wb_clk_i, arst_i, , , , , , );


--A1L100 is prer~266
--operation mode is normal

A1L100 = wb_rst_i # wb_dat_i[0];


--A1L75 is prer[4]~267
--operation mode is normal

A1L75 = wb_rst_i # !wb_adr_i[0] & !wb_adr_i[1] & A1L123;


--wb_wacc is wb_wacc
--operation mode is normal

wb_wacc = wb_stb_i & wb_cyc_i & wb_we_i;


--A1L31 is always3~14
--operation mode is normal

A1L31 = wb_adr_i[0] # wb_adr_i[1] # !ctr[7] # !wb_adr_i[2];


--A1L35 is cr[0]~456
--operation mode is normal

A1L35 = wb_rst_i # !A1L31 # !wb_wacc;


--A1L86 is prer[9]~268
--operation mode is normal

A1L86 = wb_rst_i # !wb_adr_i[1] & wb_adr_i[0] & A1L123;


--C1_dout is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|dout
--operation mode is normal

C1_dout_lut_out = C1_sSCL & C1_dout # !C1_sSCL & (C1_dSCL & (!C1_sSDA) # !C1_dSCL & C1_dout);
C1_dout = DFFEAS(C1_dout_lut_out, wb_clk_i, VCC, , , , , , );


--B1_ld is i2c_master_byte_ctrl:byte_controller|ld
--operation mode is normal

B1_ld_lut_out = B1L5 & (B1L49 # B1L47 & !B1_c_state.ST_IDLE);
B1_ld = DFFEAS(B1_ld_lut_out, wb_clk_i, arst_i, , , , , , );


--B1_shift is i2c_master_byte_ctrl:byte_controller|shift
--operation mode is normal

B1_shift_lut_out = B1L5 & C1_cmd_ack & (B1_c_state.ST_READ # B1L52);
B1_shift = DFFEAS(B1_shift_lut_out, wb_clk_i, arst_i, , , , , , );


--B1L44 is i2c_master_byte_ctrl:byte_controller|dcnt[0]~174
--operation mode is normal

B1L44 = wb_rst_i # B1_ld # B1_shift;


--A1L57 is ctr~204
--operation mode is normal

A1L57 = wb_dat_i[1] & (!wb_rst_i);


--A1L101 is prer~269
--operation mode is normal

A1L101 = wb_rst_i # wb_dat_i[1];


--A1L58 is ctr~205
--operation mode is normal

A1L58 = wb_dat_i[2] & (!wb_rst_i);


--A1L102 is prer~270
--operation mode is normal

A1L102 = wb_rst_i # wb_dat_i[2];


--A1L59 is ctr~206
--operation mode is normal

A1L59 = wb_dat_i[3] & (!wb_rst_i);


--A1L45 is cr~459
--operation mode is normal

A1L45 = A1L31 & cr[3] # !A1L31 & (wb_dat_i[3]);


--A1L131 is wb_ack_o~0
--operation mode is normal

A1L131 = wb_stb_i & wb_cyc_i;


--A1L103 is prer~271
--operation mode is normal

A1L103 = wb_rst_i # wb_dat_i[3];


--A1L60 is ctr~207
--operation mode is normal

A1L60 = wb_dat_i[4] & (!wb_rst_i);


--A1L43 is cr[7]~461
--operation mode is normal

A1L43 = wb_wacc & A1L31 # !wb_wacc & (!C1_al & !B1_cmd_ack);


--A1L44 is cr[7]~462
--operation mode is normal

A1L44 = wb_rst_i # !A1L43;


--A1L104 is prer~272
--operation mode is normal

A1L104 = wb_rst_i # wb_dat_i[4];


--A1L61 is ctr~208
--operation mode is normal

A1L61 = wb_dat_i[5] & (!wb_rst_i);


--A1L105 is prer~273
--operation mode is normal

A1L105 = wb_rst_i # wb_dat_i[5];


--C1_sto_condition is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sto_condition