i2c_master_top.tan.rpt

verilog在cpld上实现i2c主从设备通讯功能

+------------------------------+-------+---------------+----------------------------------+------------------+--------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; wb_clk_i        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'wb_clk_i'                                                                                                                                                                                                                                                                                                                                                       ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                            ; To                                                                              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 183.18 MHz ( period = 5.459 ns )                    ; cr[5]                                                                           ; i2c_master_byte_ctrl:byte_controller|core_cmd[3]                                ; wb_clk_i   ; wb_clk_i ; None                        ; None                      ; 5.185 ns                ;
; N/A                                     ; 187.34 MHz ( period = 5.338 ns )                    ; cr[5]                                                                           ; i2c_master_byte_ctrl:byte_controller|core_cmd[2]                                ; wb_clk_i   ; wb_clk_i ; None                        ; None                      ; 5.171 ns                ;
; N/A                                     ; 191.46 MHz ( period = 5.223 ns )                    ; cr[6]                                                                           ; i2c_master_byte_ctrl:byte_controller|core_cmd[3]                                ; wb_clk_i   ; wb_clk_i ; None                        ; None                      ; 5.057 ns                ;
; N/A                                     ; 193.80 MHz ( period = 5.160 ns )                    ; i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[6]  ; i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[7]  ; wb_clk_i   ; wb_clk_i ; None                        ; None                      ; 4.994 ns                ;
; N/A                                     ; 193.80 MHz ( period = 5.160 ns )                    ; i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[6]  ; i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[6]  ; wb_clk_i   ; wb_clk_i ; None                        ; None                      ; 4.994 ns                ;
; N/A                                     ; 193.80 MHz ( period = 5.160 ns )                    ; i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[6]  ; i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[5]  ; wb_clk_i   ; wb_clk_i ; None                        ; None                      ; 4.994 ns                ;
; N/A                                     ; 193.80 MHz ( period = 5.160 ns )                    ; i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[6]  ; i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[2]  ; wb_clk_i   ; wb_clk_i ; None                        ; None                      ; 4.994 ns                ;