i2c_master_top.map.qmsg

verilog在cpld上实现i2c主从设备通讯功能

{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state " "Info: Selected Auto state machine encoding method for state machine \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state " "Info: Encoding result for state machine \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|c_state.ST_IDLE " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|c_state.ST_IDLE\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|c_state.ST_STOP " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|c_state.ST_STOP\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|c_state.ST_ACK " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|c_state.ST_ACK\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|c_state.ST_WRITE " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|c_state.ST_WRITE\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|c_state.ST_READ " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|c_state.ST_READ\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|c_state.ST_START " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|c_state.ST_START\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_IDLE 000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_IDLE\" uses code string \"000000\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_STOP 110000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_STOP\" uses code string \"110000\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_WRITE 100100 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_WRITE\" uses code string \"100100\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_READ 100010 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_READ\" uses code string \"100010\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_START 100001 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_START\" uses code string \"100001\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_ACK 101000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state.ST_ACK\" uses code string \"101000\"" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state " "Info: Selected Auto state machine encoding method for state machine \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state " "Info: Encoding result for state machine \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "18 " "Info: Completed encoding using 18 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.idle " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.idle\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_d " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_d\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_c " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_c\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_b " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_b\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_a " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_a\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_d " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_d\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_c " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_c\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_b " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_b\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_a " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_a\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_d " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_d\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_c " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_c\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_b " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_b\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_a " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_a\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_e " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_e\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_d " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_d\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_c " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_c\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_b " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_b\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_a " "Info: Encoded state bit \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_a\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.idle 000000000000000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.idle\" uses code string \"000000000000000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_c 101000000000000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_c\" uses code string \"101000000000000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_b 100100000000000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_b\" uses code string \"100100000000000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_d 100001000000000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_d\" uses code string \"100001000000000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_c 100000100000000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_c\" uses code string \"100000100000000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_b 100000010000000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_b\" uses code string \"100000010000000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_d 100000000100000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_d\" uses code string \"100000000100000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_c 100000000010000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_c\" uses code string \"100000000010000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_b 100000000001000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_b\" uses code string \"100000000001000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_e 100000000000010000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_e\" uses code string \"100000000000010000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_d 100000000000001000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_d\" uses code string \"100000000000001000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_c 100000000000000100 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_c\" uses code string \"100000000000000100\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_b 100000000000000010 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_b\" uses code string \"100000000000000010\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_a 100000001000000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.rd_a\" uses code string \"100000001000000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_a 100010000000000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_a\" uses code string \"100010000000000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_a 100000000000100000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.stop_a\" uses code string \"100000000000100000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_a 100000000000000001 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.start_a\" uses code string \"100000000000000001\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_d 110000000000000000 " "Info: State \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state.wr_d\" uses code string \"110000000000000000\"" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "scl_pad_o GND " "Warning: Pin \"scl_pad_o\" stuck at GND" {  } { { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 40 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sda_pad_o GND " "Warning: Pin \"sda_pad_o\" stuck at GND" {  } { { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 45 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 84 -1 0 } } { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 88 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 108 -1 0 } } { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 99 -1 0 } } { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 96 -1 0 } } { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 96 -1 0 } } { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 147 -1 0 } } { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 147 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "300 " "Info: Implemented 300 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "267 " "Info: Implemented 267 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 18 17:18:51 2007 " "Info: Processing ended: Sun Nov 18 17:18:51 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}