i2c_master_top.map.qmsg

verilog在cpld上实现i2c主从设备通讯功能

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tst_bench_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file tst_bench_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 tst_bench_top " "Info: Found entity 1: tst_bench_top" {  } { { "tst_bench_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/tst_bench_top.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "i2c_master_top " "Info: Elaborating entity \"i2c_master_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c_master_top.v(122) " "Warning (10270): Verilog HDL statement warning at i2c_master_top.v(122): incomplete Case Statement has no default case item" {  } { { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 122 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 i2c_master_top.v(146) " "Warning (10230): Verilog HDL assignment warning at i2c_master_top.v(146): truncated value with size 2 to match size of target (1)" {  } { { "i2c_master_top.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 146 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_master_byte_ctrl i2c_master_byte_ctrl:byte_controller " "Info: Elaborating entity \"i2c_master_byte_ctrl\" for hierarchy \"i2c_master_byte_ctrl:byte_controller\"" {  } { { "i2c_master_top.v" "byte_controller" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_top.v" 163 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_master_bit_ctrl i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller " "Info: Elaborating entity \"i2c_master_bit_ctrl\" for hierarchy \"i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\"" {  } { { "i2c_master_byte_ctrl.v" "bit_controller" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c_master_bit_ctrl.v(288) " "Info (10264): Verilog HDL Case Statement information at i2c_master_bit_ctrl.v(288): all case item expressions in this case statement are onehot" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 288 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state 6 " "Info: State machine \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|c_state\" contains 6 states" {  } { { "i2c_master_byte_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_byte_ctrl.v" 133 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state 18 " "Info: State machine \"\|i2c_master_top\|i2c_master_byte_ctrl:byte_controller\|i2c_master_bit_ctrl:bit_controller\|c_state\" contains 18 states" {  } { { "i2c_master_bit_ctrl.v" "" { Text "D:/My Docu/CPLD/i2c Sample/i2c_master_bit_ctrl.v" 260 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}