i2c_master_top.fit.summary

来自「verilog在cpld上实现i2c主从设备通讯功能」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Sun Nov 18 17:19:09 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : i2c_master_top
Top-level Entity Name : i2c_master_top
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 252 / 10,570 ( 2 % )
Total pins : 33 / 336 ( 10 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )