i2c_master_top.tan.summary

来自「verilog在cpld上实现i2c主从设备通讯功能」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.700 ns
From           : wb_cyc_i
To             : cr[6]
From Clock     : --
To Clock       : wb_clk_i
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.614 ns
From           : wb_dat_o[2]~reg0
To             : wb_dat_o[2]
From Clock     : wb_clk_i
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.105 ns
From           : wb_stb_i
To             : wb_ack_o~reg0
From Clock     : --
To Clock       : wb_clk_i
Failed Paths   : 0

Type           : Clock Setup: 'wb_clk_i'
Slack          : N/A
Required Time  : None
Actual Time    : 183.18 MHz ( period = 5.459 ns )
From           : cr[5]
To             : i2c_master_byte_ctrl:byte_controller|core_cmd[3]
From Clock     : wb_clk_i
To Clock       : wb_clk_i
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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