i2c_master_top.fit.eqn

verilog在cpld上实现i2c主从设备通讯功能

C1_cmd_ack = DFFEAS(C1_cmd_ack_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1_c_state.ST_ACK is i2c_master_byte_ctrl:byte_controller|c_state.ST_ACK at LC_X34_Y20_N6
--operation mode is normal

B1_c_state.ST_ACK_lut_out = B1L5 & (B1L14 # B1L15 & !B1L28);
B1_c_state.ST_ACK = DFFEAS(B1_c_state.ST_ACK_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1_c_state.ST_READ is i2c_master_byte_ctrl:byte_controller|c_state.ST_READ at LC_X34_Y18_N9
--operation mode is normal

B1_c_state.ST_READ_lut_out = B1L5 & (B1L20 # !B1L15 & B1_c_state.ST_READ);
B1_c_state.ST_READ = DFFEAS(B1_c_state.ST_READ_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1L1 is i2c_master_byte_ctrl:byte_controller|Select~459 at LC_X35_Y17_N2
--operation mode is normal

B1L1 = C1_cmd_ack & (B1_c_state.ST_ACK # !B1_c_state.ST_READ) # !C1_cmd_ack & !B1_c_state.ST_ACK;


--B1L41 is i2c_master_byte_ctrl:byte_controller|core_txd~259 at LC_X35_Y17_N1
--operation mode is normal

B1L41 = B1L1 & (B1_sr[7] # B1_c_state.ST_ACK) # !B1L1 & cr[3];


--C1_c_state.stop_c is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.stop_c at LC_X33_Y19_N2
--operation mode is normal

C1_c_state.stop_c_lut_out = B1L5 & (C1_clk_en & C1_c_state.stop_c # !C1_clk_en & (C1_c_state.stop_b));
C1_c_state.stop_c = DFFEAS(C1_c_state.stop_c_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1L2 is i2c_master_byte_ctrl:byte_controller|Select~460 at LC_X35_Y18_N5
--operation mode is normal

B1L2 = C1_cmd_ack & (B1_c_state.ST_ACK);


--B1L47 is i2c_master_byte_ctrl:byte_controller|go~44 at LC_X35_Y18_N4
--operation mode is normal

B1L47 = !B1_cmd_ack & (cr[5] # cr[6] # cr[4]);


--B1_c_state.ST_IDLE is i2c_master_byte_ctrl:byte_controller|c_state.ST_IDLE at LC_X34_Y21_N5
--operation mode is normal

B1_c_state.ST_IDLE_lut_out = B1L5 & !B1L17 & (B1L47 # B1_c_state.ST_IDLE);
B1_c_state.ST_IDLE = DFFEAS(B1_c_state.ST_IDLE_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1L3 is i2c_master_byte_ctrl:byte_controller|Select~461 at LC_X35_Y18_N2
--operation mode is normal

B1L3 = B1L47 & (!B1_c_state.ST_IDLE);


--B1L22 is i2c_master_byte_ctrl:byte_controller|cmd_ack~55 at LC_X34_Y19_N3
--operation mode is normal

B1L22 = !cr[5] & !cr[4] & !cr[7];


--C1_dSCL is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|dSCL at LC_X33_Y21_N5
--operation mode is normal

C1_dSCL_lut_out = !wb_rst_i & C1_sSCL;
C1_dSCL = DFFEAS(C1_dSCL_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1_c_state.ST_START is i2c_master_byte_ctrl:byte_controller|c_state.ST_START at LC_X34_Y18_N2
--operation mode is normal

B1_c_state.ST_START_lut_out = B1L5 & (B1L18 # cr[7] & B1L3);
B1_c_state.ST_START = DFFEAS(B1_c_state.ST_START_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1L49 is i2c_master_byte_ctrl:byte_controller|ld~90 at LC_X33_Y18_N8
--operation mode is normal

B1L49 = C1_cmd_ack & B1_c_state.ST_START;


--B1_c_state.ST_WRITE is i2c_master_byte_ctrl:byte_controller|c_state.ST_WRITE at LC_X34_Y18_N0
--operation mode is normal

B1_c_state.ST_WRITE_lut_out = B1L5 & (B1L19 # !B1L15 & B1_c_state.ST_WRITE);
B1_c_state.ST_WRITE = DFFEAS(B1_c_state.ST_WRITE_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1_dcnt[2] is i2c_master_byte_ctrl:byte_controller|dcnt[2] at LC_X34_Y17_N4
--operation mode is normal

B1_dcnt[2]_lut_out = !wb_rst_i & (B1_ld # B1L50 $ B1_dcnt[2]);
B1_dcnt[2] = DFFEAS(B1_dcnt[2]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , , );


--B1_dcnt[1] is i2c_master_byte_ctrl:byte_controller|dcnt[1] at LC_X34_Y17_N1
--operation mode is normal

B1_dcnt[1]_lut_out = !wb_rst_i & (B1_ld # B1_dcnt[0] $ !B1_dcnt[1]);
B1_dcnt[1] = DFFEAS(B1_dcnt[1]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , , );


--B1_dcnt[0] is i2c_master_byte_ctrl:byte_controller|dcnt[0] at LC_X34_Y17_N0
--operation mode is normal

B1_dcnt[0]_lut_out = !wb_rst_i & (B1_ld # !B1_dcnt[0]);
B1_dcnt[0] = DFFEAS(B1_dcnt[0]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , , );


--B1L52 is i2c_master_byte_ctrl:byte_controller|shift~98 at LC_X34_Y17_N2
--operation mode is normal

B1L52 = B1_c_state.ST_WRITE & (B1_dcnt[2] # B1_dcnt[0] # B1_dcnt[1]);


--C1_dSDA is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|dSDA at LC_X35_Y19_N0
--operation mode is normal

C1_dSDA_lut_out = C1_sSDA & !wb_rst_i;
C1_dSDA = DFFEAS(C1_dSDA_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1L32 is i2c_master_byte_ctrl:byte_controller|core_cmd~1548 at LC_X33_Y18_N1
--operation mode is normal

B1L32 = B1_c_state.ST_IDLE & (B1_core_cmd[0]) # !B1_c_state.ST_IDLE & (B1L47 & (cr[7]) # !B1L47 & B1_core_cmd[0]);


--B1L28 is i2c_master_byte_ctrl:byte_controller|core_cmd[3]~1550 at LC_X34_Y18_N7
--operation mode is normal

B1L28 = !B1_c_state.ST_READ & (!B1_c_state.ST_WRITE);


--B1L29 is i2c_master_byte_ctrl:byte_controller|core_cmd[3]~1551 at LC_X34_Y18_N8
--operation mode is normal

B1L29 = B1_c_state.ST_READ # B1_c_state.ST_START & (!B1_c_state.ST_WRITE);


--B1L33 is i2c_master_byte_ctrl:byte_controller|core_cmd~1552 at LC_X33_Y20_N3
--operation mode is normal

B1L33 = B1L28 & cr[5] & (B1L29 # !cr[7]);


--B1L50 is i2c_master_byte_ctrl:byte_controller|reduce_or~24 at LC_X34_Y17_N9
--operation mode is normal

B1L50 = !B1_dcnt[1] & !B1_dcnt[0];


--B1L30 is i2c_master_byte_ctrl:byte_controller|core_cmd[3]~1553 at LC_X34_Y18_N1
--operation mode is normal

B1L30 = !B1_c_state.ST_START & !B1_c_state.ST_READ & (!B1_c_state.ST_WRITE);


--B1L34 is i2c_master_byte_ctrl:byte_controller|core_cmd~1555 at LC_X34_Y21_N1
--operation mode is normal

B1L34 = B1_c_state.ST_IDLE & (C1_cmd_ack) # !B1_c_state.ST_IDLE & B1L47 # !B1L5;


--B1L35 is i2c_master_byte_ctrl:byte_controller|core_cmd~1556 at LC_X34_Y18_N4
--operation mode is normal

B1L35 = B1L29 $ (B1L50 & !B1_dcnt[2] & !B1L28);


--B1L36 is i2c_master_byte_ctrl:byte_controller|core_cmd~1557 at LC_X34_Y18_N5
--operation mode is normal

B1L36 = cr[5] & (B1L35) # !cr[5] & cr[4] & !cr[7] & !B1L35;


--B1_c_state.ST_STOP is i2c_master_byte_ctrl:byte_controller|c_state.ST_STOP at LC_X34_Y19_N6
--operation mode is normal

B1_c_state.ST_STOP_lut_out = B1L5 & (!C1_cmd_ack & B1_c_state.ST_STOP # !B1L13);
B1_c_state.ST_STOP = DFFEAS(B1_c_state.ST_STOP_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1L37 is i2c_master_byte_ctrl:byte_controller|core_cmd~1559 at LC_X34_Y19_N2
--operation mode is normal

B1L37 = B1_c_state.ST_ACK # B1_c_state.ST_STOP # !B1L30;


--B1L38 is i2c_master_byte_ctrl:byte_controller|core_cmd~1560 at LC_X34_Y19_N9
--operation mode is normal

B1L38 = B1_c_state.ST_IDLE & (!C1_cmd_ack & B1L37) # !B1_c_state.ST_IDLE & (!C1_cmd_ack & B1L37 # !B1L47);


--B1L12 is i2c_master_byte_ctrl:byte_controller|c_state~1082 at LC_X34_Y20_N0
--operation mode is normal

B1L12 = C1_cmd_ack & B1_c_state.ST_ACK & (cr[6]);


--B1L13 is i2c_master_byte_ctrl:byte_controller|c_state~1083 at LC_X34_Y19_N5
--operation mode is normal

B1L13 = !B1L12 & (B1_c_state.ST_IDLE # !B1L22 # !B1L47);


--C1_cmd_stop is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cmd_stop at LC_X33_Y21_N0
--operation mode is normal

C1_cmd_stop_lut_out = !B1_core_cmd[2] & !B1_core_cmd[3] & !B1_core_cmd[0] & B1_core_cmd[1];
C1_cmd_stop = DFFEAS(C1_cmd_stop_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , wb_rst_i, );


--C1_c_state.start_c is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.start_c at LC_X32_Y20_N0
--operation mode is normal

C1_c_state.start_c_lut_out = B1L5 & (C1_clk_en & (C1_c_state.start_c) # !C1_clk_en & C1_c_state.start_b);
C1_c_state.start_c = DFFEAS(C1_c_state.start_c_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1L87 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|cnt[15]~709 at LC_X40_Y20_N8
--operation mode is normal

C1L87 = wb_rst_i # !C1_sSCL # !C1_dscl_oen # !C1L6;


--B1L14 is i2c_master_byte_ctrl:byte_controller|c_state~1084 at LC_X34_Y20_N1
--operation mode is normal

B1L14 = B1_c_state.ST_ACK & (!C1_cmd_ack);


--B1L15 is i2c_master_byte_ctrl:byte_controller|c_state~1085 at LC_X34_Y20_N9
--operation mode is normal

B1L15 = C1_cmd_ack & !B1_dcnt[2] & !B1_dcnt[0] & !B1_dcnt[1];


--B1L16 is i2c_master_byte_ctrl:byte_controller|c_state~1087 at LC_X33_Y18_N0
--operation mode is normal

B1L16 = !B1_cmd_ack & (!cr[7] & !B1_c_state.ST_IDLE);


--C1_c_state.stop_b is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.stop_b at LC_X33_Y19_N9
--operation mode is normal

C1_c_state.stop_b_lut_out = B1L5 & (C1_clk_en & (C1_c_state.stop_b) # !C1_clk_en & C1_c_state.stop_a);
C1_c_state.stop_b = DFFEAS(C1_c_state.stop_b_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1L17 is i2c_master_byte_ctrl:byte_controller|c_state~1089 at LC_X34_Y21_N4
--operation mode is normal

B1L17 = C1_cmd_ack & (B1_c_state.ST_STOP # !cr[6] & B1_c_state.ST_ACK);


--B1L18 is i2c_master_byte_ctrl:byte_controller|c_state~1091 at LC_X33_Y18_N2
--operation mode is normal

B1L18 = B1_c_state.ST_IDLE & (!C1_cmd_ack & B1_c_state.ST_START);


--B1L19 is i2c_master_byte_ctrl:byte_controller|c_state~1093 at LC_X34_Y18_N6
--operation mode is normal

B1L19 = !cr[5] & (B1L49 # cr[4] & B1L16);


--B1L39 is i2c_master_byte_ctrl:byte_controller|core_cmd~1562 at LC_X33_Y20_N1
--operation mode is normal

B1L39 = B1L29 $ (!B1_dcnt[2] & !B1_dcnt[1] & !B1_dcnt[0]);


--B1L31 is i2c_master_byte_ctrl:byte_controller|core_cmd[3]~1563 at LC_X34_Y21_N9
--operation mode is normal

B1L31 = C1_al # wb_rst_i # B1_c_state.ST_IDLE & B1L30;


--B1L20 is i2c_master_byte_ctrl:byte_controller|c_state~1096 at LC_X33_Y18_N6
--operation mode is normal

B1L20 = cr[5] & (B1L16 # C1_cmd_ack & B1_c_state.ST_START);


--wb_adr_i[0] is wb_adr_i[0] at PIN_H2
--operation mode is input

wb_adr_i[0] = INPUT();


--wb_adr_i[2] is wb_adr_i[2] at PIN_AA8
--operation mode is input

wb_adr_i[2] = INPUT();


--wb_adr_i[1] is wb_adr_i[1] at PIN_E9
--operation mode is input

wb_adr_i[1] = INPUT();


--wb_clk_i is wb_clk_i at PIN_L2
--operation mode is input

wb_clk_i = INPUT();


--wb_stb_i is wb_stb_i at PIN_M2
--operation mode is input

wb_stb_i = INPUT();


--wb_cyc_i is wb_cyc_i at PIN_U9
--operation mode is input

wb_cyc_i = INPUT();


--arst_i is arst_i at PIN_L3
--operation mode is input

arst_i = INPUT();


--wb_rst_i is wb_rst_i at PIN_K8
--operation mode is input

wb_rst_i = INPUT();


--wb_dat_i[0] is wb_dat_i[0] at PIN_J3
--operation mode is input

wb_dat_i[0] = INPUT();


--wb_we_i is wb_we_i at PIN_F9
--operation mode is input

wb_we_i = INPUT();


--wb_dat_i[1] is wb_dat_i[1] at PIN_J9
--operation mode is input

wb_dat_i[1] = INPUT();


--wb_dat_i[2] is wb_dat_i[2] at PIN_H21
--operation mode is input

wb_dat_i[2] = INPUT();


--wb_dat_i[3] is wb_dat_i[3] at PIN_G8
--operation mode is input

wb_dat_i[3] = INPUT();


--wb_dat_i[4] is wb_dat_i[4] at PIN_J8
--operation mode is input

wb_dat_i[4] = INPUT();


--wb_dat_i[5] is wb_dat_i[5] at PIN_D8
--operation mode is input

wb_dat_i[5] = INPUT();


--wb_dat_i[6] is wb_d