i2c_master_top.fit.eqn

verilog在cpld上实现i2c主从设备通讯功能

A1L108 = C1_al # wb_rst_i # !C1_clk_en;


--C1L99 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_oen~205 at LC_X32_Y21_N3
--operation mode is normal

C1L99 = !C1_sda_oen & (C1_clk_en # !C1_c_state.idle) # !B1L5;


--B1_core_txd is i2c_master_byte_ctrl:byte_controller|core_txd at LC_X35_Y17_N3
--operation mode is normal

B1_core_txd_lut_out = !C1_al & B1L41 & !wb_rst_i;
B1_core_txd = DFFEAS(B1_core_txd_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_c_state.wr_b is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.wr_b at LC_X32_Y21_N7
--operation mode is normal

C1_c_state.wr_b_lut_out = B1L5 & (C1_clk_en & C1_c_state.wr_b # !C1_clk_en & (C1_c_state.wr_a));
C1_c_state.wr_b = DFFEAS(C1_c_state.wr_b_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_c_state.wr_c is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.wr_c at LC_X32_Y21_N0
--operation mode is normal

C1_c_state.wr_c_lut_out = B1L5 & (C1_clk_en & (C1_c_state.wr_c) # !C1_clk_en & C1_c_state.wr_b);
C1_c_state.wr_c = DFFEAS(C1_c_state.wr_c_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--A1L110 is rtl~99 at LC_X32_Y21_N6
--operation mode is normal

A1L110 = !C1_c_state.wr_b & !C1_c_state.wr_c;


--C1L100 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_oen~206 at LC_X32_Y21_N1
--operation mode is normal

C1L100 = B1_core_txd & (C1_c_state.wr_a # C1_c_state.wr_d # !A1L110);


--C1_c_state.start_b is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.start_b at LC_X32_Y20_N3
--operation mode is normal

C1_c_state.start_b_lut_out = B1L5 & (C1_clk_en & C1_c_state.start_b # !C1_clk_en & (C1_c_state.start_a));
C1_c_state.start_b = DFFEAS(C1_c_state.start_b_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_c_state.stop_d is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.stop_d at LC_X33_Y19_N8
--operation mode is normal

C1_c_state.stop_d_lut_out = B1L5 & (C1_clk_en & C1_c_state.stop_d # !C1_clk_en & (C1_c_state.stop_c));
C1_c_state.stop_d = DFFEAS(C1_c_state.stop_d_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_c_state.rd_b is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.rd_b at LC_X33_Y19_N6
--operation mode is normal

C1_c_state.rd_b_lut_out = B1L5 & (C1_clk_en & (C1_c_state.rd_b) # !C1_clk_en & C1_c_state.rd_a);
C1_c_state.rd_b = DFFEAS(C1_c_state.rd_b_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_c_state.rd_c is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.rd_c at LC_X33_Y19_N4
--operation mode is normal

C1_c_state.rd_c_lut_out = B1L5 & (C1_clk_en & C1_c_state.rd_c # !C1_clk_en & (C1_c_state.rd_b));
C1_c_state.rd_c = DFFEAS(C1_c_state.rd_c_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1L101 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_oen~207 at LC_X33_Y20_N0
--operation mode is normal

C1L101 = C1_c_state.rd_c # C1_c_state.rd_b;


--C1L102 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_oen~208 at LC_X33_Y20_N4
--operation mode is normal

C1L102 = C1_c_state.start_b # C1_c_state.stop_d # C1L101 # !C1L10;


--A1L56 is ctr~202 at LC_X36_Y21_N3
--operation mode is normal

A1L56 = !wb_rst_i & wb_dat_i[0];


--A1L123 is txr[2]~133 at LC_X36_Y17_N5
--operation mode is normal

A1L123 = wb_stb_i & !wb_adr_i[2] & wb_cyc_i & wb_we_i;


--A1L124 is txr[2]~134 at LC_X36_Y17_N1
--operation mode is normal

A1L124 = wb_rst_i # wb_adr_i[0] & wb_adr_i[1] & A1L123;


--A1L55 is ctr[7]~203 at LC_X36_Y17_N2
--operation mode is normal

A1L55 = wb_rst_i # !wb_adr_i[0] & wb_adr_i[1] & A1L123;


--B1_cmd_ack is i2c_master_byte_ctrl:byte_controller|cmd_ack at LC_X35_Y18_N3
--operation mode is normal

B1_cmd_ack_lut_out = B1L5 & (B1L2 # B1L3 & B1L22);
B1_cmd_ack = DFFEAS(B1_cmd_ack_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--A1L100 is prer~266 at LC_X36_Y21_N1
--operation mode is normal

A1L100 = wb_rst_i # wb_dat_i[0];


--A1L75 is prer[4]~267 at LC_X36_Y17_N6
--operation mode is normal

A1L75 = wb_rst_i # !wb_adr_i[0] & !wb_adr_i[1] & A1L123;


--wb_wacc is wb_wacc at LC_X36_Y16_N5
--operation mode is normal

wb_wacc = wb_stb_i & (wb_cyc_i & wb_we_i);


--A1L31 is always3~14 at LC_X36_Y19_N8
--operation mode is normal

A1L31 = wb_adr_i[0] # wb_adr_i[1] # !ctr[7] # !wb_adr_i[2];


--A1L35 is cr[0]~456 at LC_X36_Y21_N7
--operation mode is normal

A1L35 = wb_rst_i # !A1L31 # !wb_wacc;


--A1L86 is prer[9]~268 at LC_X36_Y17_N8
--operation mode is normal

A1L86 = wb_rst_i # wb_adr_i[0] & !wb_adr_i[1] & A1L123;


--C1_dout is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|dout at LC_X33_Y21_N3
--operation mode is normal

C1_dout_lut_out = C1_dSCL & (C1_sSCL & (C1_dout) # !C1_sSCL & !C1_sSDA) # !C1_dSCL & (C1_dout);
C1_dout = DFFEAS(C1_dout_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--B1_ld is i2c_master_byte_ctrl:byte_controller|ld at LC_X34_Y17_N8
--operation mode is normal

B1_ld_lut_out = B1L5 & (B1L49 # !B1_c_state.ST_IDLE & B1L47);
B1_ld = DFFEAS(B1_ld_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1_shift is i2c_master_byte_ctrl:byte_controller|shift at LC_X34_Y17_N3
--operation mode is normal

B1_shift_lut_out = B1L5 & C1_cmd_ack & (B1L52 # B1_c_state.ST_READ);
B1_shift = DFFEAS(B1_shift_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1L44 is i2c_master_byte_ctrl:byte_controller|dcnt[0]~174 at LC_X34_Y17_N5
--operation mode is normal

B1L44 = wb_rst_i # B1_shift # B1_ld;


--A1L57 is ctr~204 at LC_X36_Y21_N6
--operation mode is normal

A1L57 = !wb_rst_i & (wb_dat_i[1]);


--A1L101 is prer~269 at LC_X33_Y21_N4
--operation mode is normal

A1L101 = wb_dat_i[1] # wb_rst_i;


--A1L58 is ctr~205 at LC_X36_Y21_N5
--operation mode is normal

A1L58 = !wb_rst_i & wb_dat_i[2];


--A1L102 is prer~270 at LC_X36_Y21_N4
--operation mode is normal

A1L102 = wb_rst_i # wb_dat_i[2];


--A1L59 is ctr~206 at LC_X35_Y21_N2
--operation mode is normal

A1L59 = !wb_rst_i & (wb_dat_i[3]);


--A1L45 is cr~459 at LC_X35_Y17_N6
--operation mode is normal

A1L45 = A1L31 & (cr[3]) # !A1L31 & wb_dat_i[3];


--A1L131 is wb_ack_o~0 at LC_X36_Y16_N2
--operation mode is normal

A1L131 = wb_cyc_i & wb_stb_i;


--A1L103 is prer~271 at LC_X39_Y19_N1
--operation mode is normal

A1L103 = wb_rst_i # wb_dat_i[3];


--A1L60 is ctr~207 at LC_X35_Y20_N3
--operation mode is normal

A1L60 = !wb_rst_i & (wb_dat_i[4]);


--A1L43 is cr[7]~461 at LC_X36_Y19_N3
--operation mode is normal

A1L43 = wb_wacc & (A1L31) # !wb_wacc & !B1_cmd_ack & !C1_al;


--A1L44 is cr[7]~462 at LC_X34_Y19_N0
--operation mode is normal

A1L44 = wb_rst_i # !A1L43;


--A1L104 is prer~272 at LC_X35_Y20_N4
--operation mode is normal

A1L104 = wb_rst_i # wb_dat_i[4];


--A1L61 is ctr~208 at LC_X39_Y19_N7
--operation mode is normal

A1L61 = !wb_rst_i & (wb_dat_i[5]);


--A1L105 is prer~273 at LC_X39_Y19_N8
--operation mode is normal

A1L105 = wb_rst_i # wb_dat_i[5];


--C1_sto_condition is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sto_condition at LC_X35_Y19_N4
--operation mode is normal

C1_sto_condition_lut_out = C1_dSDA & !C1_sSDA & !C1_sSCL;
C1_sto_condition = DFFEAS(C1_sto_condition_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , wb_rst_i, );


--C1_sta_condition is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sta_condition at LC_X35_Y19_N9
--operation mode is normal

C1_sta_condition_lut_out = !C1_dSDA & C1_sSDA & !C1_sSCL;
C1_sta_condition = DFFEAS(C1_sta_condition_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , wb_rst_i, );


--A1L62 is ctr~209 at LC_X33_Y21_N9
--operation mode is normal

A1L62 = !wb_rst_i & wb_dat_i[6];


--A1L106 is prer~274 at LC_X39_Y19_N4
--operation mode is normal

A1L106 = wb_rst_i # wb_dat_i[6];


--A1L63 is ctr~210 at LC_X40_Y19_N4
--operation mode is normal

A1L63 = !wb_rst_i & wb_dat_i[7];


--B1_ack_out is i2c_master_byte_ctrl:byte_controller|ack_out at LC_X35_Y18_N0
--operation mode is normal

B1_ack_out_lut_out = B1L5 & (B1L2 & (C1_dout) # !B1L2 & B1_ack_out);
B1_ack_out = DFFEAS(B1_ack_out_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--A1L107 is prer~275 at LC_X40_Y19_N1
--operation mode is normal

A1L107 = wb_rst_i # wb_dat_i[7];


--B1_core_cmd[0] is i2c_master_byte_ctrl:byte_controller|core_cmd[0] at LC_X33_Y18_N7
--operation mode is normal

B1_core_cmd[0]_lut_out = B1L32 & B1L5 & (!B1_c_state.ST_IDLE # !C1_cmd_ack);
B1_core_cmd[0] = DFFEAS(B1_core_cmd[0]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--B1_core_cmd[3] is i2c_master_byte_ctrl:byte_controller|core_cmd[3] at LC_X33_Y20_N5
--operation mode is normal

B1_core_cmd[3]_lut_out = !B1L31 & (B1L33 # B1L39 & !B1L28);
B1_core_cmd[3] = DFFEAS(B1_core_cmd[3]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L34, , , , );


--B1_core_cmd[2] is i2c_master_byte_ctrl:byte_controller|core_cmd[2] at LC_X34_Y18_N3
--operation mode is normal

B1_core_cmd[2]_lut_out = !B1L31 & (B1L35 $ (B1L36 # !B1L28));
B1_core_cmd[2] = DFFEAS(B1_core_cmd[2]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L34, , , , );


--B1_core_cmd[1] is i2c_master_byte_ctrl:byte_controller|core_cmd[1] at LC_X34_Y19_N4
--operation mode is normal

B1_core_cmd[1]_lut_out = B1L5 & (B1_core_cmd[1] & B1L38 # !B1L13);
B1_core_cmd[1] = DFFEAS(B1_core_cmd[1]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1L1 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|Decoder~128 at LC_X33_Y20_N2
--operation mode is normal

C1L1 = !B1_core_cmd[1] & !B1_core_cmd[3] & B1_core_cmd[0] & !B1_core_cmd[2];


--C1L29 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state~1596 at LC_X33_Y20_N6
--operation mode is normal

C1L29 = C1_clk_en & (C1_c_state.start_a) # !C1_clk_en & !C1_c_state.idle & (C1L1);


--C1L30 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state~1597 at LC_X34_Y20_N2
--operation mode is normal

C1L30 = B1_core_cmd[3] & (B1_core_cmd[0] # B1_core_cmd[2] # B1_core_cmd[1]) # !B1_core_cmd[3] & (B1_core_cmd[0] & (B1_core_cmd[2] # B1_core_cmd[1]) # !B1_core_cmd[0] & (B1_core_cmd[2] $ !B1_core_cmd[1]));


--C1L31 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state~1598 at LC_X34_Y20_N5
--operation mode is normal

C1L31 = !C1_c_state.idle & (C1_clk_en # C1L30);


--C1L93 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|reduce_or~31 at LC_X34_Y20_N7
--operation mode is normal

C1L93 = C1_c_state.rd_d # C1_c_state.start_e # C1_c_state.wr_d # C1_c_state.stop_d;


--C1_sda_chk is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_chk at LC_X34_Y21_N0
--operation mode is normal

C1_sda_chk_lut_out = !C1_al & !wb_rst_i & (C1_c_state.wr_b # C1_c_state.wr_c);
C1_sda_chk = DFFEAS(C1_sda_chk_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L108, , , , );


--C1_sSDA is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sSDA at LC_X33_Y21_N8
--operation mode is normal

C1_sSDA_lut_out = !wb_rst_i & !sda_pad_i;
C1_sSDA = DFFEAS(C1_sSDA_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1L7 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|al~49 at LC_X34_Y21_N6
--operation mode is normal

C1L7 = C1_sSDA & (!C1_sda_oen & C1_sda_chk);


--C1_dcmd_stop is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|dcmd_stop at LC_X33_Y21_N7
--operation mode is normal