i2c_master_top.fit.eqn

verilog在cpld上实现i2c主从设备通讯功能

A1L14 = A1L13 & (B1_sr[3] # !wb_adr_i[0]) # !A1L13 & !prer[11] & wb_adr_i[0];


--cr[4] is cr[4] at LC_X34_Y19_N1
--operation mode is normal

cr[4]_lut_out = wb_dat_i[4] & !wb_rst_i & wb_wacc;
cr[4] = DFFEAS(cr[4]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L44, , , , );


--A1L15 is Select~933 at LC_X35_Y20_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[4]_qfbk = txr[4];
A1L15 = wb_adr_i[0] & (txr[4]_qfbk) # !wb_adr_i[0] & (cr[4]);

--txr[4] is txr[4] at LC_X35_Y20_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[4] = DFFEAS(A1L15, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L124, A1L60, , , VCC);


--prer[12] is prer[12] at LC_X35_Y20_N0
--operation mode is normal

prer[12]_lut_out = !A1L104;
prer[12] = DFFEAS(prer[12]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L86, , , , );


--prer[4] is prer[4] at LC_X39_Y21_N2
--operation mode is normal

prer[4]_lut_out = !A1L104;
prer[4] = DFFEAS(prer[4]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L75, , , , );


--A1L16 is Select~934 at LC_X35_Y21_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[4]_qfbk = ctr[4];
A1L16 = wb_adr_i[0] & (wb_adr_i[1]) # !wb_adr_i[0] & (wb_adr_i[1] & (ctr[4]_qfbk) # !wb_adr_i[1] & !prer[4]);

--ctr[4] is ctr[4] at LC_X35_Y21_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[4] = DFFEAS(A1L16, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L55, A1L60, , , VCC);


--B1_sr[4] is i2c_master_byte_ctrl:byte_controller|sr[4] at LC_X35_Y17_N0
--operation mode is normal

B1_sr[4]_lut_out = B1_ld & (txr[4]) # !B1_ld & B1_sr[3];
B1_sr[4] = DFFEAS(B1_sr[4]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , wb_rst_i, );


--A1L17 is Select~935 at LC_X35_Y17_N8
--operation mode is normal

A1L17 = wb_adr_i[0] & (A1L16 & (B1_sr[4]) # !A1L16 & !prer[12]) # !wb_adr_i[0] & (A1L16);


--al is al at LC_X35_Y19_N7
--operation mode is normal

al_lut_out = C1_al # !cr[7] & al;
al = DFFEAS(al_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , wb_rst_i, );


--prer[5] is prer[5] at LC_X36_Y19_N9
--operation mode is normal

prer[5]_lut_out = !A1L105;
prer[5] = DFFEAS(prer[5]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L75, , , , );


--A1L18 is Select~937 at LC_X36_Y19_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[5]_qfbk = ctr[5];
A1L18 = wb_adr_i[2] & wb_adr_i[1] # !wb_adr_i[2] & (wb_adr_i[1] & ctr[5]_qfbk # !wb_adr_i[1] & (!prer[5]));

--ctr[5] is ctr[5] at LC_X36_Y19_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[5] = DFFEAS(A1L18, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L55, A1L61, , , VCC);


--cr[5] is cr[5] at LC_X34_Y19_N8
--operation mode is normal

cr[5]_lut_out = wb_dat_i[5] & wb_wacc & !wb_rst_i;
cr[5] = DFFEAS(cr[5]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L44, , , , );


--A1L19 is Select~938 at LC_X36_Y18_N1
--operation mode is normal

A1L19 = wb_adr_i[2] & (A1L18 & (cr[5]) # !A1L18 & al) # !wb_adr_i[2] & A1L18;


--prer[13] is prer[13] at LC_X39_Y19_N6
--operation mode is normal

prer[13]_lut_out = !A1L105;
prer[13] = DFFEAS(prer[13]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L86, , , , );


--A1L20 is Select~939 at LC_X36_Y18_N4
--operation mode is normal

A1L20 = A1L150 & (!A1L151) # !A1L150 & (A1L151 & (!prer[13]) # !A1L151 & A1L19);


--B1_sr[5] is i2c_master_byte_ctrl:byte_controller|sr[5] at LC_X35_Y17_N7
--operation mode is normal

B1_sr[5]_lut_out = B1_ld & txr[5] # !B1_ld & (B1_sr[4]);
B1_sr[5] = DFFEAS(B1_sr[5]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , wb_rst_i, );


--A1L21 is Select~940 at LC_X36_Y18_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[5]_qfbk = txr[5];
A1L21 = A1L150 & (A1L20 & (B1_sr[5]) # !A1L20 & txr[5]_qfbk) # !A1L150 & A1L20;

--txr[5] is txr[5] at LC_X36_Y18_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[5] = DFFEAS(A1L21, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L124, A1L61, , , VCC);


--C1_busy is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|busy at LC_X35_Y19_N8
--operation mode is normal

C1_busy_lut_out = !C1_sto_condition & (C1_busy # C1_sta_condition);
C1_busy = DFFEAS(C1_busy_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , wb_rst_i, );


--prer[6] is prer[6] at LC_X36_Y19_N0
--operation mode is normal

prer[6]_lut_out = !A1L106;
prer[6] = DFFEAS(prer[6]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L75, , , , );


--A1L22 is Select~942 at LC_X36_Y19_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[6]_qfbk = ctr[6];
A1L22 = wb_adr_i[2] & wb_adr_i[1] # !wb_adr_i[2] & (wb_adr_i[1] & ctr[6]_qfbk # !wb_adr_i[1] & (!prer[6]));

--ctr[6] is ctr[6] at LC_X36_Y19_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[6] = DFFEAS(A1L22, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L55, A1L62, , , VCC);


--cr[6] is cr[6] at LC_X34_Y20_N4
--operation mode is normal

cr[6]_lut_out = wb_wacc & wb_dat_i[6] & (!wb_rst_i);
cr[6] = DFFEAS(cr[6]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L44, , , , );


--A1L23 is Select~943 at LC_X36_Y19_N4
--operation mode is normal

A1L23 = wb_adr_i[2] & (A1L22 & (cr[6]) # !A1L22 & C1_busy) # !wb_adr_i[2] & (A1L22);


--prer[14] is prer[14] at LC_X39_Y19_N9
--operation mode is normal

prer[14]_lut_out = !A1L106;
prer[14] = DFFEAS(prer[14]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L86, , , , );


--A1L24 is Select~944 at LC_X36_Y18_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[6]_qfbk = txr[6];
A1L24 = A1L151 & (A1L150 & (txr[6]_qfbk) # !A1L150 & !prer[14]) # !A1L151 & (A1L150);

--txr[6] is txr[6] at LC_X36_Y18_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[6] = DFFEAS(A1L24, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L124, A1L62, , , VCC);


--B1_sr[6] is i2c_master_byte_ctrl:byte_controller|sr[6] at LC_X35_Y17_N5
--operation mode is normal

B1_sr[6]_lut_out = B1_ld & txr[6] # !B1_ld & (B1_sr[5]);
B1_sr[6] = DFFEAS(B1_sr[6]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , wb_rst_i, );


--A1L25 is Select~945 at LC_X36_Y18_N7
--operation mode is normal

A1L25 = A1L24 & (A1L151 # B1_sr[6]) # !A1L24 & A1L23 & !A1L151;


--rxack is rxack at LC_X35_Y18_N8
--operation mode is normal

rxack_lut_out = !wb_rst_i & (B1_ack_out);
rxack = DFFEAS(rxack_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--prer[7] is prer[7] at LC_X40_Y19_N0
--operation mode is normal

prer[7]_lut_out = !A1L107;
prer[7] = DFFEAS(prer[7]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L75, , , , );


--A1L26 is Select~947 at LC_X36_Y19_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[7]_qfbk = ctr[7];
A1L26 = wb_adr_i[2] & wb_adr_i[1] # !wb_adr_i[2] & (wb_adr_i[1] & ctr[7]_qfbk # !wb_adr_i[1] & (!prer[7]));

--ctr[7] is ctr[7] at LC_X36_Y19_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[7] = DFFEAS(A1L26, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L55, A1L63, , , VCC);


--cr[7] is cr[7] at LC_X34_Y19_N7
--operation mode is normal

cr[7]_lut_out = wb_dat_i[7] & wb_wacc & !wb_rst_i;
cr[7] = DFFEAS(cr[7]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L44, , , , );


--A1L27 is Select~948 at LC_X35_Y18_N6
--operation mode is normal

A1L27 = wb_adr_i[2] & (A1L26 & cr[7] # !A1L26 & (rxack)) # !wb_adr_i[2] & A1L26;


--prer[15] is prer[15] at LC_X40_Y19_N2
--operation mode is normal

prer[15]_lut_out = !A1L107;
prer[15] = DFFEAS(prer[15]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L86, , , , );


--A1L28 is Select~949 at LC_X35_Y18_N9
--operation mode is normal

A1L28 = A1L151 & !prer[15] & !A1L150 # !A1L151 & (A1L150 # A1L27);


--B1_sr[7] is i2c_master_byte_ctrl:byte_controller|sr[7] at LC_X35_Y17_N9
--operation mode is normal

B1_sr[7]_lut_out = B1_ld & txr[7] # !B1_ld & (B1_sr[6]);
B1_sr[7] = DFFEAS(B1_sr[7]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , wb_rst_i, );


--A1L29 is Select~950 at LC_X35_Y18_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[7]_qfbk = txr[7];
A1L29 = A1L150 & (A1L28 & B1_sr[7] # !A1L28 & (txr[7]_qfbk)) # !A1L150 & (A1L28);

--txr[7] is txr[7] at LC_X35_Y18_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[7] = DFFEAS(A1L29, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L124, A1L63, , , VCC);


--C1_c_state.start_a is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.start_a at LC_X33_Y20_N9
--operation mode is normal

C1_c_state.start_a_lut_out = !C1_al & !wb_rst_i & C1L29;
C1_c_state.start_a = DFFEAS(C1_c_state.start_a_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_c_state.idle is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.idle at LC_X34_Y20_N3
--operation mode is normal

C1_c_state.idle_lut_out = !C1L31 & B1L5 & (C1_clk_en # !C1L93);
C1_c_state.idle = DFFEAS(C1_c_state.idle_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_al is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|al at LC_X34_Y21_N2
--operation mode is normal

C1_al_lut_out = C1L7 # !C1_dcmd_stop & C1_sto_condition;
C1_al = DFFEAS(C1_al_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , wb_rst_i, );


--B1L5 is i2c_master_byte_ctrl:byte_controller|always2~37 at LC_X34_Y21_N7
--operation mode is normal

B1L5 = !wb_rst_i & !C1_al;


--A1L109 is rtl~97 at LC_X32_Y20_N1
--operation mode is normal

A1L109 = !C1_scl_oen & (C1_c_state.start_a # !C1_c_state.idle) # !B1L5;


--C1_c_state.rd_a is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.rd_a at LC_X33_Y18_N5
--operation mode is normal

C1_c_state.rd_a_lut_out = !wb_rst_i & !C1_al & (C1L32);
C1_c_state.rd_a = DFFEAS(C1_c_state.rd_a_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_c_state.rd_d is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.rd_d at LC_X33_Y20_N7
--operation mode is normal

C1_c_state.rd_d_lut_out = B1L5 & (C1_clk_en & C1_c_state.rd_d # !C1_clk_en & (C1_c_state.rd_c));
C1_c_state.rd_d = DFFEAS(C1_c_state.rd_d_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1L10 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.idle~57 at LC_X33_Y20_N8
--operation mode is normal

C1L10 = !C1_c_state.start_a & !C1_c_state.rd_d & !C1_c_state.rd_a;


--C1_c_state.start_e is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.start_e at LC_X32_Y20_N8
--operation mode is normal

C1_c_state.start_e_lut_out = B1L5 & (C1_clk_en & (C1_c_state.start_e) # !C1_clk_en & C1_c_state.start_d);
C1_c_state.start_e = DFFEAS(C1_c_state.start_e_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_c_state.wr_d is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.wr_d at LC_X32_Y21_N5
--operation mode is normal

C1_c_state.wr_d_lut_out = B1L5 & (C1_clk_en & C1_c_state.wr_d # !C1_clk_en & (C1_c_state.wr_c));
C1_c_state.wr_d = DFFEAS(C1_c_state.wr_d_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_c_state.wr_a is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.wr_a at LC_X32_Y21_N9
--operation mode is normal

C1_c_state.wr_a_lut_out = !C1_al & !wb_rst_i & (C1L33);
C1_c_state.wr_a = DFFEAS(C1_c_state.wr_a_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1L11 is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.idle~58 at LC_X32_Y20_N6
--operation mode is normal

C1L11 = !C1_c_state.start_e & C1_c_state.idle & !C1_c_state.wr_d & !C1_c_state.wr_a;


--C1_c_state.stop_a is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|c_state.stop_a at LC_X32_Y20_N4
--operation mode is normal

C1_c_state.stop_a_lut_out = !wb_rst_i & !C1_al & (C1L34);
C1_c_state.stop_a = DFFEAS(C1_c_state.stop_a_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--C1_clk_en is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|clk_en at LC_X34_Y21_N8
--operation mode is normal

C1_clk_en_lut_out = !wb_rst_i & (C1_dscl_oen & C1_sSCL # !C1L6);
C1_clk_en = DFFEAS(C1_clk_en_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--A1L108 is rtl~2 at LC_X34_Y21_N3
--operation mode is normal