i2c_master_top.fit.eqn

verilog在cpld上实现i2c主从设备通讯功能

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--A1L152Q is wb_dat_o[0]~reg0 at LC_X36_Y17_N4
--operation mode is normal

A1L152Q_lut_out = A1L4 & (!wb_adr_i[0] # !wb_adr_i[2] # !wb_adr_i[1]);
A1L152Q = DFFEAS(A1L152Q_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--A1L154Q is wb_dat_o[1]~reg0 at LC_X36_Y18_N0
--operation mode is normal

A1L154Q_lut_out = A1L8 & (!wb_adr_i[0] # !wb_adr_i[1] # !wb_adr_i[2]);
A1L154Q = DFFEAS(A1L154Q_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--A1L156Q is wb_dat_o[2]~reg0 at LC_X35_Y21_N8
--operation mode is normal

A1L156Q_lut_out = wb_adr_i[2] & (A1L160 & A1L9) # !wb_adr_i[2] & A1L11;
A1L156Q = DFFEAS(A1L156Q_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--A1L158Q is wb_dat_o[3]~reg0 at LC_X35_Y21_N3
--operation mode is normal

A1L158Q_lut_out = wb_adr_i[2] & A1L12 & A1L160 # !wb_adr_i[2] & (A1L14);
A1L158Q = DFFEAS(A1L158Q_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--A1L161Q is wb_dat_o[4]~reg0 at LC_X35_Y21_N0
--operation mode is normal

A1L161Q_lut_out = wb_adr_i[2] & A1L160 & (A1L15) # !wb_adr_i[2] & (A1L17);
A1L161Q = DFFEAS(A1L161Q_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--A1L163Q is wb_dat_o[5]~reg0 at LC_X36_Y18_N3
--operation mode is normal

A1L163Q_lut_out = A1L21 & (!wb_adr_i[0] # !wb_adr_i[1] # !wb_adr_i[2]);
A1L163Q = DFFEAS(A1L163Q_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--A1L165Q is wb_dat_o[6]~reg0 at LC_X36_Y17_N0
--operation mode is normal

A1L165Q_lut_out = A1L25 & (!wb_adr_i[1] # !wb_adr_i[0] # !wb_adr_i[2]);
A1L165Q = DFFEAS(A1L165Q_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--A1L167Q is wb_dat_o[7]~reg0 at LC_X35_Y18_N1
--operation mode is normal

A1L167Q_lut_out = A1L29 & (!wb_adr_i[0] # !wb_adr_i[1] # !wb_adr_i[2]);
A1L167Q = DFFEAS(A1L167Q_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--A1L132Q is wb_ack_o~reg0 at LC_X36_Y16_N4
--operation mode is normal

A1L132Q_lut_out = !A1L132Q & (wb_cyc_i & wb_stb_i);
A1L132Q = DFFEAS(A1L132Q_lut_out, GLOBAL(wb_clk_i), VCC, , , , , , );


--A1L169Q is wb_inta_o~reg0 at LC_X35_Y19_N3
--operation mode is normal

A1L169Q_lut_out = irq_flag & (ctr[6]);
A1L169Q = DFFEAS(A1L169Q_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , wb_rst_i, );


--C1_scl_oen is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|scl_oen at LC_X32_Y20_N2
--operation mode is normal

C1_scl_oen_lut_out = !A1L109 & (C1_c_state.stop_a # !C1L10 # !C1L11);
C1_scl_oen = DFFEAS(C1_scl_oen_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L108, , , , );


--C1_sda_oen is i2c_master_byte_ctrl:byte_controller|i2c_master_bit_ctrl:bit_controller|sda_oen at LC_X32_Y21_N4
--operation mode is normal

C1_sda_oen_lut_out = !C1L99 & (C1_clk_en # !C1L102 & !C1L100);
C1_sda_oen = DFFEAS(C1_sda_oen_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--A1L150 is wb_dat_o[0]~162 at LC_X36_Y18_N8
--operation mode is normal

A1L150 = wb_adr_i[0] & (wb_adr_i[2] # wb_adr_i[1]);


--irq_flag is irq_flag at LC_X35_Y19_N6
--operation mode is normal

irq_flag_lut_out = !cr[0] & (irq_flag # C1_al # B1_cmd_ack);
irq_flag = DFFEAS(irq_flag_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , wb_rst_i, );


--prer[0] is prer[0] at LC_X36_Y20_N6
--operation mode is normal

prer[0]_lut_out = !A1L100;
prer[0] = DFFEAS(prer[0]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L75, , , , );


--A1L1 is Select~915 at LC_X36_Y20_N4
--operation mode is normal

A1L1 = wb_adr_i[2] & (irq_flag # wb_adr_i[1]) # !wb_adr_i[2] & (!wb_adr_i[1] & !prer[0]);


--cr[0] is cr[0] at LC_X36_Y21_N9
--operation mode is normal

cr[0]_lut_out = wb_wacc & !wb_rst_i & wb_dat_i[0];
cr[0] = DFFEAS(cr[0]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L35, , , , );


--A1L2 is Select~916 at LC_X36_Y20_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[0]_qfbk = ctr[0];
A1L2 = A1L1 & (cr[0] # !wb_adr_i[1]) # !A1L1 & wb_adr_i[1] & ctr[0]_qfbk;

--ctr[0] is ctr[0] at LC_X36_Y20_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[0] = DFFEAS(A1L2, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L55, A1L56, , , VCC);


--A1L151 is wb_dat_o[0]~163 at LC_X36_Y17_N7
--operation mode is normal

A1L151 = !wb_adr_i[1] & wb_adr_i[0];


--prer[8] is prer[8] at LC_X35_Y20_N9
--operation mode is normal

prer[8]_lut_out = !A1L100;
prer[8] = DFFEAS(prer[8]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L86, , , , );


--A1L3 is Select~917 at LC_X36_Y17_N9
--operation mode is normal

A1L3 = A1L151 & !A1L150 & (!prer[8]) # !A1L151 & (A1L150 # A1L2);


--B1_sr[0] is i2c_master_byte_ctrl:byte_controller|sr[0] at LC_X34_Y17_N7
--operation mode is normal

B1_sr[0]_lut_out = B1_ld & txr[0] # !B1_ld & (C1_dout);
B1_sr[0] = DFFEAS(B1_sr[0]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , wb_rst_i, );


--A1L4 is Select~918 at LC_X36_Y17_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[0]_qfbk = txr[0];
A1L4 = A1L3 & (B1_sr[0] # !A1L150) # !A1L3 & (txr[0]_qfbk & A1L150);

--txr[0] is txr[0] at LC_X36_Y17_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[0] = DFFEAS(A1L4, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L124, A1L56, , , VCC);


--tip is tip at LC_X35_Y19_N5
--operation mode is normal

tip_lut_out = !wb_rst_i & (cr[5] # cr[4]);
tip = DFFEAS(tip_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , , );


--prer[1] is prer[1] at LC_X36_Y20_N0
--operation mode is normal

prer[1]_lut_out = !A1L101;
prer[1] = DFFEAS(prer[1]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L75, , , , );


--A1L5 is Select~920 at LC_X36_Y20_N5
--operation mode is normal

A1L5 = wb_adr_i[2] & (tip # wb_adr_i[1]) # !wb_adr_i[2] & (!wb_adr_i[1] & !prer[1]);


--cr[1] is cr[1] at LC_X36_Y21_N2
--operation mode is normal

cr[1]_lut_out = wb_dat_i[1] & !wb_rst_i & wb_wacc;
cr[1] = DFFEAS(cr[1]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L35, , , , );


--A1L6 is Select~921 at LC_X36_Y20_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[1]_qfbk = ctr[1];
A1L6 = wb_adr_i[1] & (A1L5 & cr[1] # !A1L5 & (ctr[1]_qfbk)) # !wb_adr_i[1] & (A1L5);

--ctr[1] is ctr[1] at LC_X36_Y20_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[1] = DFFEAS(A1L6, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L55, A1L57, , , VCC);


--prer[9] is prer[9] at LC_X35_Y20_N6
--operation mode is normal

prer[9]_lut_out = !A1L101;
prer[9] = DFFEAS(prer[9]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L86, , , , );


--A1L7 is Select~922 at LC_X36_Y18_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[1]_qfbk = txr[1];
A1L7 = A1L151 & (A1L150 & (txr[1]_qfbk) # !A1L150 & !prer[9]) # !A1L151 & (A1L150);

--txr[1] is txr[1] at LC_X36_Y18_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[1] = DFFEAS(A1L7, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L124, A1L57, , , VCC);


--B1_sr[1] is i2c_master_byte_ctrl:byte_controller|sr[1] at LC_X34_Y17_N6
--operation mode is normal

B1_sr[1]_lut_out = B1_ld & txr[1] # !B1_ld & (B1_sr[0]);
B1_sr[1] = DFFEAS(B1_sr[1]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , wb_rst_i, );


--A1L8 is Select~923 at LC_X36_Y18_N2
--operation mode is normal

A1L8 = A1L7 & (A1L151 # B1_sr[1]) # !A1L7 & A1L6 & !A1L151;


--cr[2] is cr[2] at LC_X36_Y21_N0
--operation mode is normal

cr[2]_lut_out = wb_wacc & !wb_rst_i & wb_dat_i[2];
cr[2] = DFFEAS(cr[2]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L35, , , , );


--A1L9 is Select~925 at LC_X36_Y21_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[2]_qfbk = txr[2];
A1L9 = wb_adr_i[0] & txr[2]_qfbk # !wb_adr_i[0] & (cr[2]);

--txr[2] is txr[2] at LC_X36_Y21_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[2] = DFFEAS(A1L9, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L124, A1L58, , , VCC);


--A1L160 is wb_dat_o[4]~164 at LC_X35_Y21_N6
--operation mode is normal

A1L160 = wb_adr_i[0] $ wb_adr_i[1];


--prer[10] is prer[10] at LC_X40_Y19_N6
--operation mode is normal

prer[10]_lut_out = !A1L102;
prer[10] = DFFEAS(prer[10]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L86, , , , );


--prer[2] is prer[2] at LC_X40_Y19_N9
--operation mode is normal

prer[2]_lut_out = !A1L102;
prer[2] = DFFEAS(prer[2]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L75, , , , );


--A1L10 is Select~926 at LC_X36_Y20_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[2]_qfbk = ctr[2];
A1L10 = wb_adr_i[1] & (ctr[2]_qfbk # wb_adr_i[0]) # !wb_adr_i[1] & !prer[2] & (!wb_adr_i[0]);

--ctr[2] is ctr[2] at LC_X36_Y20_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[2] = DFFEAS(A1L10, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L55, A1L58, , , VCC);


--B1_sr[2] is i2c_master_byte_ctrl:byte_controller|sr[2] at LC_X35_Y19_N2
--operation mode is normal

B1_sr[2]_lut_out = B1_ld & (txr[2]) # !B1_ld & B1_sr[1];
B1_sr[2] = DFFEAS(B1_sr[2]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , wb_rst_i, );


--A1L11 is Select~927 at LC_X36_Y20_N3
--operation mode is normal

A1L11 = A1L10 & (B1_sr[2] # !wb_adr_i[0]) # !A1L10 & (wb_adr_i[0] & !prer[10]);


--cr[3] is cr[3] at LC_X35_Y17_N4
--operation mode is normal

cr[3]_lut_out = A1L131 & (wb_we_i & (A1L45) # !wb_we_i & cr[3]) # !A1L131 & cr[3];
cr[3] = DFFEAS(cr[3]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , , , , wb_rst_i, );


--A1L12 is Select~929 at LC_X35_Y20_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[3]_qfbk = txr[3];
A1L12 = wb_adr_i[0] & (txr[3]_qfbk) # !wb_adr_i[0] & (cr[3]);

--txr[3] is txr[3] at LC_X35_Y20_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

txr[3] = DFFEAS(A1L12, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L124, A1L59, , , VCC);


--prer[11] is prer[11] at LC_X39_Y19_N5
--operation mode is normal

prer[11]_lut_out = !A1L103;
prer[11] = DFFEAS(prer[11]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L86, , , , );


--prer[3] is prer[3] at LC_X39_Y19_N2
--operation mode is normal

prer[3]_lut_out = !A1L103;
prer[3] = DFFEAS(prer[3]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L75, , , , );


--A1L13 is Select~930 at LC_X35_Y21_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[3]_qfbk = ctr[3];
A1L13 = wb_adr_i[0] & (wb_adr_i[1]) # !wb_adr_i[0] & (wb_adr_i[1] & (ctr[3]_qfbk) # !wb_adr_i[1] & !prer[3]);

--ctr[3] is ctr[3] at LC_X35_Y21_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

ctr[3] = DFFEAS(A1L13, GLOBAL(wb_clk_i), GLOBAL(arst_i), , A1L55, A1L59, , , VCC);


--B1_sr[3] is i2c_master_byte_ctrl:byte_controller|sr[3] at LC_X35_Y19_N1
--operation mode is normal

B1_sr[3]_lut_out = B1_ld & (txr[3]) # !B1_ld & B1_sr[2];
B1_sr[3] = DFFEAS(B1_sr[3]_lut_out, GLOBAL(wb_clk_i), GLOBAL(arst_i), , B1L44, , , wb_rst_i, );


--A1L14 is Select~931 at LC_X35_Y21_N7
--operation mode is normal