swepfre.mrp

这是我的毕业设计

Release 7.1i Map H.38
Xilinx Mapping Report File for Design 'swepfre'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -ise d:\rfid\rfid_re\rfid_re.ise
-intstyle ise -p xc4vsx55-ff1148-10 -cm area -pr b -k 4 -c 100 -o
swepfre_map.ncd swepfre.ngd swepfre.pcf 
Target Device  : xc4vsx55
Target Package : ff1148
Target Speed   : -10
Mapper Version : virtex4 -- $Revision: 1.26.6.3 $
Mapped Date    : Fri Oct 05 14:45:26 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:   21
Logic Utilization:
  Number of Slice Flip Flops:          60 out of  49,152    1%
  Number of 4 input LUTs:              86 out of  49,152    1%
Logic Distribution:
  Number of occupied Slices:                           55 out of  24,576    1%
    Number of Slices containing only related logic:      55 out of      55  100%
    Number of Slices containing unrelated logic:          0 out of      55    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             95 out of  49,152    1%
  Number used as logic:                 86
  Number used as a route-thru:           9
  Number of bonded IOBs:                8 out of     640    1%
  Number of BUFG/BUFGCTRLs:             2 out of      32    6%
    Number used as BUFGs:                2
    Number used as BUFGCTRLs:            0
  Number of FIFO16/RAMB16s:             1 out of     320    1%
    Number used as FIFO16s:              0
    Number used as RAMB16s:              1
  Number of DCM_ADVs:                   1 out of       8   12%

Total equivalent gate count for design:  1,245
Additional JTAG gate count for IOBs:  384
Peak Memory Usage:  232 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKFX_1> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKOUT_1> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKFX_2> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKOUT_2> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKFX_3> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKOUT_3> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKFX_4> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKOUT_4> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKFX_5> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKOUT_5> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKFX_6> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKOUT_6> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKFX_7> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <XIL_ML_UNUSED_DCM_CLKOUT_7> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules - Dangling pins on
   block:<XIL_ML_UNUSED_DCM_1/XIL_ML_UNUSED_DCM_1>:<DCM_ADV_DCM_ADV>.
   For VARIABLE or DIRECT phase shifting the phase shift pins PSEN PSCLK and
   PSDONE should be connected to active signals.
WARNING:PhysDesignRules - Dangling pins on
   block:<XIL_ML_UNUSED_DCM_2/XIL_ML_UNUSED_DCM_2>:<DCM_ADV_DCM_ADV>.
   For VARIABLE or DIRECT phase shifting the phase shift pins PSEN PSCLK and
   PSDONE should be connected to active signals.
WARNING:PhysDesignRules - Dangling pins on
   block:<XIL_ML_UNUSED_DCM_3/XIL_ML_UNUSED_DCM_3>:<DCM_ADV_DCM_ADV>.
   For VARIABLE or DIRECT phase shifting the phase shift pins PSEN PSCLK and
   PSDONE should be connected to active signals.
WARNING:PhysDesignRules - Dangling pins on
   block:<XIL_ML_UNUSED_DCM_4/XIL_ML_UNUSED_DCM_4>:<DCM_ADV_DCM_ADV>.
   For VARIABLE or DIRECT phase shifting the phase shift pins PSEN PSCLK and
   PSDONE should be connected to active signals.
WARNING:PhysDesignRules - Dangling pins on
   block:<XIL_ML_UNUSED_DCM_5/XIL_ML_UNUSED_DCM_5>:<DCM_ADV_DCM_ADV>.
   For VARIABLE or DIRECT phase shifting the phase shift pins PSEN PSCLK and
   PSDONE should be connected to active signals.
WARNING:PhysDesignRules - Dangling pins on
   block:<XIL_ML_UNUSED_DCM_6/XIL_ML_UNUSED_DCM_6>:<DCM_ADV_DCM_ADV>.
   For VARIABLE or DIRECT phase shifting the phase shift pins PSEN PSCLK and
   PSDONE should be connected to active signals.
WARNING:PhysDesignRules - Dangling pins on
   block:<XIL_ML_UNUSED_DCM_7/XIL_ML_UNUSED_DCM_7>:<DCM_ADV_DCM_ADV>.
   For VARIABLE or DIRECT phase shifting the phase shift pins PSEN PSCLK and
   PSDONE should be connected to active signals.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.
INFO:PhysDesignRules:727 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM_ADV comp
   XIL_ML_UNUSED_DCM_1/XIL_ML_UNUSED_DCM_1, consult the device Interactive Data
   Sheet.
INFO:PhysDesignRules:727 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM_ADV comp
   XIL_ML_UNUSED_DCM_2/XIL_ML_UNUSED_DCM_2, consult the device Interactive Data
   Sheet.
INFO:PhysDesignRules:727 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM_ADV comp
   XIL_ML_UNUSED_DCM_3/XIL_ML_UNUSED_DCM_3, consult the device Interactive Data
   Sheet.
INFO:PhysDesignRules:727 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM_ADV comp
   XIL_ML_UNUSED_DCM_4/XIL_ML_UNUSED_DCM_4, consult the device Interactive Data
   Sheet.
INFO:PhysDesignRules:727 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM_ADV comp
   XIL_ML_UNUSED_DCM_5/XIL_ML_UNUSED_DCM_5, consult the device Interactive Data
   Sheet.
INFO:PhysDesignRules:727 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM_ADV comp
   XIL_ML_UNUSED_DCM_6/XIL_ML_UNUSED_DCM_6, consult the device Interactive Data
   Sheet.
INFO:PhysDesignRules:727 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM_ADV comp
   XIL_ML_UNUSED_DCM_7/XIL_ML_UNUSED_DCM_7, consult the device Interactive Data
   Sheet.
INFO:PhysDesignRules:727 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM_ADV comp
   XLXI_10/DCM_ADV_INST/XLXI_10/DCM_ADV_INST, consult the device Interactive
   Data Sheet.

Section 4 - Removed Logic Summary
---------------------------------
   1 block(s) removed
   3 block(s) optimized away
   1 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic reported below is either:
   1. part of a cycle
   2. part of disabled logic
   3. a side-effect of other trimmed logic

The signal "XLXI_86/mid_result_0_rt/O" is unused and has been removed.
 Unused block "XLXI_86/mid_result_0_rt" (ROM) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC
MUXCY 		XLXI_86/swep_fre__n0008<0>cy

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |             | Strength | Rate |              |          | Delay    |
+----------------------------------------------------------------------------------------------------------------------------------------+
| clk40                              | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| clk120                             | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| sin_out<0>                         | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| sin_out<1>                         | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| sin_out<2>                         | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| sin_out<3>                         | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| sin_out<4>                         | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
| sin_out<5>                         | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
+----------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
--------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 8
Number of Equivalent Gates for Design = 1,245
Number of RPM Macros = 0
Number of Hard Macros = 0
PMV = 0
USR_ACCESS_VIRTEX4 = 0
BUFIO = 0
GT11CLK = 0
GT11 = 0
IDELAYCTRL = 0
FRAME_ECC_VIRTEX4 = 0
STARTUP_VIRTEX4 = 0
JTAGPPC = 0
ICAP_VIRTEX4 = 0
DPM = 0
DCI_TEST = 0
DCIRESET = 0
CAPTURE_VIRTEX4 = 0
BSCAN_VIRTEX4 = 0
OSERDES = 0
ISERDES = 0
BUFR = 0
EMAC = 0
PPC405_ADV = 0
MONITOR = 0
PMCD = 0
DCM_ADV = 1
DSP48 = 0
Unbonded IOBs = 0
Bonded IOBs = 8
XORs = 42
CARRY_INITs = 22
CARRY_SKIPs = 0
CARRY_MUXes = 41
Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MUXFs = 0
MULT_ANDs = 0
4 input LUTs used as Route-Thrus = 9
4 input LUTs = 86
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 20
Slice Flip Flops = 60
SliceMs = 0
SliceLs = 55
Slices = 55
F6 Muxes = 0
F5 Muxes = 0
F8 Muxes = 0
F7 Muxes = 0
Number of LUT signals with 4 loads = 0
Number of LUT signals with 3 loads = 1
Number of LUT signals with 2 loads = 33
Number of LUT signals with 1 load = 45
NGM Average fanout of LUT = 2.35
NGM Maximum fanout of LUT = 34
NGM Average fanin for LUT = 2.2209
Number of LUT symbols = 86