swepfre.par

来自「这是我的毕业设计」· PAR 代码 · 共 169 行

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

408-TITI::  Fri Oct 05 14:45:43 2007

par -w -intstyle ise -ol std -t 1 swepfre_map.ncd swepfre.ncd swepfre.pcf 


Constraints file: swepfre.pcf.
Loading device for application Rf_Device from file '4vsx55.nph' in environment
C:/Xilinx.
   "swepfre" is an NCD, version 3.1, device xc4vsx55, package ff1148, speed -10
This design is using the default stepping level (major silicon revision) for
this device (0). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '1'. Additional information on "stepping
level" is available at support.xilinx.com.

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)


Device speed data version:  "ADVANCED 1.52 2005-01-22".


Device Utilization Summary:

   Number of BUFGs                     2 out of 32      6%
   Number of DCM_ADVs                  8 out of 8     100%
   Number of External IOBs             8 out of 640     1%
      Number of LOCed IOBs             8 out of 8     100%

   Number of PMVs                      1 out of 1     100%
   Number of RAMB16s                   1 out of 320     1%
   Number of Slices                   55 out of 24576   1%
      Number of SLICEMs                0 out of 12288   0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_1 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_1 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_2 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_2 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_3 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_3 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_4 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_4 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_5 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_5 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_6 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_6 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_7 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_7 has no load

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9897f9) REAL time: 8 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 8 secs 

Phase 3.2
......
.......
WARNING:Place:465 - A clock IOB component is not placed at an optimal clock IOB
   site  The clock IOB component <clk40> is placed at site IOB_X1Y75. The clock
   IO site can use the fast path between the IO and the Clock buffer/GCLK if the
   IOB is placed in the master Clock IOB Site. You may want to analyze why this
   problem exists and correct it. This is not an error so processing will
   continue.


Phase 3.2 (Checksum:990e9d) REAL time: 10 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 10 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 10 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 10 secs 

Phase 7.8
...
Phase 7.8 (Checksum:9ba7f2) REAL time: 11 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 11 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 11 secs 

Phase 10.27
Phase 10.27 (Checksum:5f5e0f6) REAL time: 11 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 11 secs 

Writing design to file swepfre.ncd


Total REAL time to Placer completion: 11 secs 
Total CPU time to Placer completion: 9 secs 

Starting Router

Phase 1: 414 unrouted;       REAL time: 14 secs 

Phase 2: 296 unrouted;       REAL time: 15 secs 

Phase 3: 68 unrouted;       REAL time: 15 secs 

Phase 4: 0 unrouted;       REAL time: 15 secs 

Total REAL time to Router completion: 15 secs 
Total CPU time to Router completion: 12 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|         clk120_OBUF | BUFGCTRL_X0Y9| No   |   30 |  0.172     |  3.676      |
+---------------------+--------------+------+------+------------+-------------+
|              XLXN_4 |         Local|      |    5 |  0.374     |  1.770      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 20 secs 
Total CPU time to PAR completion: 15 secs 

Peak Memory Usage:  212 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 15
Number of info messages: 1

Writing design to file swepfre.ncd



PAR done!