rst_gen.vhd

来自「这是我的毕业设计」· VHDL 代码 · 共 49 行

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-- Company: 
-- Engineer:
--
-- Create Date:    09:43:41 10/05/07
-- Design Name:    
-- Module Name:    rst_gen - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rst_gen is
    Port ( clk : in std_logic;
           rst : out std_logic:='0');
end rst_gen;

architecture Behavioral of rst_gen is
	 signal count:integer range 0 to 20:=0;
begin
		process(clk)
		begin
		if clk='1' and clk'event then
		if count=10 then
		rst<='1';
		count<=10;
		else  count<=count+1;
		end if;
		end if ;
		end process;

end Behavioral;