__projnav.log

这是我的毕业设计

Updating Library Versioned links
Updating Documentation files
Updating Library cache
Install complete

'\vsim.exe' 不是内部或外部命令，也不是可运行的程序
或批处理文件。
Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => vhdl
Backing up setup files if any...
Source Tools ('AUTO_DETECT') => [null]

ERROR:CAEInterfaces:326 - COMPXLIB[env]: unable to find simulator (mti_se) executables

<ToolTip>: Specify the simulator executable path in the "Simulator Path"
           property under "Compile HDL Simulation Libraries" properties.

           IMPORTANT: Make sure that the license file/other environment
           variable for mti_se are properly set

Log file (compxlib.log) generated.

ERROR: compxlib failed
Process "Compile HDL Simulation Libraries" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Compile HDL Simulation Libraries".

XILINX = 'C:\Xilinx'
Library Source => 'C:\Xilinx'

Compilation Mode = FAST
Scheduling Smart-Model library installation & compilation for VIRTEX-4 

Installing Xilinx Smart-Model.....

	-> Environment variable  LMC_HOME = c:\Xilinx\smartmodel\nt\installed_nt
	-> Extracting model names from C:\Xilinx\smartmodel\nt\image\sl_toc.dat
	-> Creating 'model.list' at current directory

Library Image directory : 'C:\Xilinx\smartmodel\nt\image'
Installaltion directory : 'c:\Xilinx\smartmodel\nt\installed_nt'
Running installer...... 

Synopsys/Logic Modeling sl_admin
Copyright (c) 1984-2000 Synopsys Inc. ALL RIGHTS RESERVED
Version: 02042

Reading Library
Reading Media
Checking user selections
Loading models....
Loading model: dcc_fpgacore_swift, version: 02401, platform: pcnt
Loading model: emac_swift, version: 01020, platform: pcnt
Loading model: glogic_adv_swift, version: 01003, platform: pcnt
Loading model: glogic_swift, version: 04000, platform: pcnt
Loading model: gt10_swift, version: 02218, platform: pcnt
Loading model: gt11_swift, version: 01009, platform: pcnt
Loading model: gt_swift, version: 01601, platform: pcnt
Loading model: ppc405_adv_swift, version: 01007, platform: pcnt
Loading model: ppc405_swift, version: 04002, platform: pcnt
Updating Configuration files
Writing: c:\Xilinx\smartmodel\nt\installed_nt/data/pcnt.lmc
Updating Library Versioned links
Updating Documentation files
Updating Library cache
Install complete

Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => vhdl
Backing up setup files if any...
Output directory => 'C:\Xilinx\vhdl\mti_se'

--> Compiling vhdl unisim library
文件名、目录名或卷标语法不正确。
    > Unisim compiled to C:\Xilinx\vhdl\mti_se\unisim
ERROR:CAEInterfaces:356 - COMPXLIB[env]: directory not accessible for writing log file 'C:\Xilinx\vhdl\mti_se\unisim\cxl_unisim.log'
<ToolTip> : check READ/WRITE permissions
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unisim]: 3 error(s), no warning(s)

ERROR:CAEInterfaces:562 - COMPXLIB[file]: unable to open info file 'C:\Xilinx\vhdl\mti_se\unisim\.xil_info'

--> Compiling vhdl simprim library
文件名、目录名或卷标语法不正确。
    > Simprim compiled to C:\Xilinx\vhdl\mti_se\simprim
ERROR:CAEInterfaces:356 - COMPXLIB[env]: directory not accessible for writing log file 'C:\Xilinx\vhdl\mti_se\simprim\cxl_simprim.log'
<ToolTip> : check READ/WRITE permissions
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[simprim]: 3 error(s), no warning(s)

ERROR:CAEInterfaces:562 - COMPXLIB[file]: unable to open info file 'C:\Xilinx\vhdl\mti_se\simprim\.xil_info'

--> Compiling vhdl XilinxCoreLib library
    > compiling unisim library first
文件名、目录名或卷标语法不正确。
    > Unisim compiled to C:\Xilinx\vhdl\mti_se\unisim
ERROR:CAEInterfaces:356 - COMPXLIB[env]: directory not accessible for writing log file 'C:\Xilinx\vhdl\mti_se\unisim\cxl_unisim.log'
<ToolTip> : check READ/WRITE permissions
    > Library mapping successful, setup file(s) modelsim.ini updated
    > [unisim]: 3 error(s), no warning(s)

ERROR:CAEInterfaces:562 - COMPXLIB[file]: unable to open info file 'C:\Xilinx\vhdl\mti_se\unisim\.xil_info'
文件名、目录名或卷标语法不正确。
    > XilinxCoreLib compiled to C:\Xilinx\vhdl\mti_se\XilinxCoreLib
ERROR:CAEInterfaces:356 - COMPXLIB[env]: directory not accessible for writing log file 'C:\Xilinx\vhdl\mti_se\XilinxCoreLib\cxl_XilinxCoreLib.log'
<ToolTip> : check READ/WRITE permissions
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[XilinxCoreLib]: 1 error(s), no warning(s)

ERROR:CAEInterfaces:562 - COMPXLIB[file]: unable to open info file 'C:\Xilinx\vhdl\mti_se\XilinxCoreLib\.xil_info'

--> Compiling vhdl smartmodel(unisim) library
    > compiling unisim library first
文件名、目录名或卷标语法不正确。
    > Unisim compiled to C:\Xilinx\vhdl\mti_se\unisim
ERROR:CAEInterfaces:356 - COMPXLIB[env]: directory not accessible for writing log file 'C:\Xilinx\vhdl\mti_se\unisim\cxl_unisim.log'
<ToolTip> : check READ/WRITE permissions
    > Library mapping successful, setup file(s) modelsim.ini updated
    > [unisim]: 3 error(s), no warning(s)

ERROR:CAEInterfaces:562 - COMPXLIB[file]: unable to open info file 'C:\Xilinx\vhdl\mti_se\unisim\.xil_info'
    > unable to parse initialization file. Check if the 
      file modelsim.ini is present in the current directory
      with read/write permissions
    > SWIFT Interface configuration procedure failed
    > Unisim Smart-Models compiled to C:\Xilinx\vhdl\mti_se\unisim
ERROR:CAEInterfaces:356 - COMPXLIB[env]: directory not accessible for writing log file 'C:\Xilinx\vhdl\mti_se\unisim\cxl_smartmodel.log'
<ToolTip> : check READ/WRITE permissions
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: 2 error(s), no warning(s)

ERROR:CAEInterfaces:562 - COMPXLIB[file]: unable to open info file 'C:\Xilinx\vhdl\mti_se\unisim\.xil_info'

--> Compiling vhdl smartmodel(simprim) library
    > compiling simprim library first
文件名、目录名或卷标语法不正确。
    > Simprim compiled to C:\Xilinx\vhdl\mti_se\simprim
ERROR:CAEInterfaces:356 - COMPXLIB[env]: directory not accessible for writing log file 'C:\Xilinx\vhdl\mti_se\simprim\cxl_simprim.log'
<ToolTip> : check READ/WRITE permissions
    > Library mapping successful, setup file(s) modelsim.ini updated
    > [simprim]: 3 error(s), no warning(s)

ERROR:CAEInterfaces:562 - COMPXLIB[file]: unable to open info file 'C:\Xilinx\vhdl\mti_se\simprim\.xil_info'
    > unable to parse initialization file. Check if the 
      file modelsim.ini is present in the current directory
      with read/write permissions
    > SWIFT Interface configuration procedure failed
    > Simprim Smart-Models compiled to C:\Xilinx\vhdl\mti_se\simprim
ERROR:CAEInterfaces:356 - COMPXLIB[env]: directory not accessible for writing log file 'C:\Xilinx\vhdl\mti_se\simprim\cxl_smartmodel.log'
<ToolTip> : check READ/WRITE permissions
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: 2 error(s), no warning(s)

ERROR:CAEInterfaces:562 - COMPXLIB[file]: unable to open info file 'C:\Xilinx\vhdl\mti_se\simprim\.xil_info'

Log file (compxlib.log) generated.

ERROR: compxlib failed
Process "Compile HDL Simulation Libraries" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Compile HDL Simulation Libraries".

XILINX = 'C:\Xilinx'
Library Source => 'C:\Xilinx'

Compilation Mode = FAST
Scheduling Smart-Model library installation & compilation for VIRTEX-4 

Installing Xilinx Smart-Model.....

	-> Environment variable  LMC_HOME = c:\Xilinx\smartmodel\nt\installed_nt
	-> Extracting model names from C:\Xilinx\smartmodel\nt\image\sl_toc.dat
	-> Creating 'model.list' at current directory

Library Image directory : 'C:\Xilinx\smartmodel\nt\image'
Installaltion directory : 'c:\Xilinx\smartmodel\nt\installed_nt'
Running installer...... 

Synopsys/Logic Modeling sl_admin
Copyright (c) 1984-2000 Synopsys Inc. ALL RIGHTS RESERVED
Version: 02042

Reading Library
Reading Media
Checking user selections
Loading models....
Loading model: dcc_fpgacore_swift, version: 02401, platform: pcnt
Loading model: emac_swift, version: 01020, platform: pcnt
Loading model: glogic_adv_swift, version: 01003, platform: pcnt
Loading model: glogic_swift, version: 04000, platform: pcnt
Loading model: gt10_swift, version: 02218, platform: pcnt
Loading model: gt11_swift, version: 01009, platform: pcnt
Loading model: gt_swift, version: 01601, platform: pcnt
Loading model: ppc405_adv_swift, version: 01007, platform: pcnt
Loading model: ppc405_swift, version: 04002, platform: pcnt
Updating Configuration files
Writing: c:\Xilinx\smartmodel\nt\installed_nt/data/pcnt.lmc
Updating Library Versioned links
Updating Documentation files
Updating Library cache
Install complete

Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => vhdl
Backing up setup files if any...
Output directory => 'C:\Xilinx\vhdl\mti_se'

--> Compiling vhdl unisim library
    > Unisim compiled to C:\Xilinx\vhdl\mti_se\unisim
    > Log file C:\Xilinx\vhdl\mti_se\unisim\cxl_unisim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[unisim]: No error(s), no warning(s)

--> Compiling vhdl simprim library
    > Simprim compiled to C:\Xilinx\vhdl\mti_se\simprim
    > Log file C:\Xilinx\vhdl\mti_se\simprim\cxl_simprim.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[simprim]: No error(s), no warning(s)

--> Compiling vhdl XilinxCoreLib library
    > XilinxCoreLib compiled to C:\Xilinx\vhdl\mti_se\XilinxCoreLib
    > Log file C:\Xilinx\vhdl\mti_se\XilinxCoreLib\cxl_XilinxCoreLib.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[XilinxCoreLib]: No error(s), no warning(s)

--> Compiling vhdl smartmodel(unisim) library
    > use -smartmodel_setup switch in case you want to configure
      the modelsim.ini for smart model usage (SWIFT Interface)
    > Unisim Smart-Models compiled to C:\Xilinx\vhdl\mti_se\unisim
    > Log file C:\Xilinx\vhdl\mti_se\unisim\cxl_smartmodel.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: No error(s), no warning(s)

--> Compiling vhdl smartmodel(simprim) library
    > use -smartmodel_setup switch in case you want to configure
      the modelsim.ini for smart model usage (SWIFT Interface)
    > Simprim Smart-Models compiled to C:\Xilinx\vhdl\mti_se\simprim
    > Log file C:\Xilinx\vhdl\mti_se\simprim\cxl_smartmodel.log generated
    > Library mapping successful, setup file(s) modelsim.ini updated

compxlib[smartmodel]: No error(s), no warning(s)

Log file (compxlib.log) generated.



Project Navigator Auto-Make Log File
-------------------------------------










Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/rfid/rfid_re/swep_fre.vhd" in Library work.
Entity <swep_fre> compiled.
Entity <swep_fre> (Architecture <behavioral>) compiled.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Create Schematic Symbol".

Compiling vhdl file "D:/rfid/rfid_re/swep_fre.vhd" in Library work.
Entity <swep_fre> compiled.
Entity <swep_fre> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.






Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.





Project Navigator Auto-Make Log File
-------------------------------------










Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/rfid/rfid_re/swep_fre.vhd" in Library work.
Entity <swep_fre> compiled.
Entity <swep_fre> (Architecture <behavioral>) compiled.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Create Schematic Symbol".

Compiling vhdl file "D:/rfid/rfid_re/swep_fre.vhd" in Library work.
Entity <swep_fre> compiled.
Entity <swep_fre> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.






Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Functional Model".

DRC Check completed: No Error found.
Vhdl netlist file generated.





Project Navigator Auto-Make Log File
-------------------------------------










Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/rfid/rfid_re/swep_fre.vhd" in Library work.
Entity <swep_fre> compiled.
ERROR:HDLParsers:164 - "D:/rfid/rfid_re/swep_fre.vhd" Line 57. parse error, unexpected IDENTIFIER, expecting SEMICOLON
ERROR:HDLParsers:164 - "D:/rfid/rfid_re/swep_fre.vhd" Line 78. parse error, unexpected IF
ERROR: XST failed
Process "Check Syntax" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Check Syntax".