__projnav.log

这是我的毕业设计

 Number of GCLKs:                        2  out of     32     6%  
 Number of DCM_ADVs:                     1  out of      8    12%  
 Number of DSP48s:                       1  out of    512     0%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+---------------------------+-------+
Clock Signal                       | Clock buffer(FF name)     | Load  |
-----------------------------------+---------------------------+-------+
clk40                              | XLXI_10/DCM_ADV_INST:CLKFX| 12    |
clk40                              | IBUFG                     | 6     |
-----------------------------------+---------------------------+-------+

Timing Summary:
---------------
Speed Grade: -11

   Minimum period: 11.172ns (Maximum Frequency: 89.509MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 5.069ns
   Maximum combinational path delay: No path found

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\rfid\rfid_re/_ngo -i -p
xc4vsx55-ff1148-11 swepfre.ngc swepfre.ngd 

Reading NGO file 'D:/rfid/rfid_re/swepfre.ngc' ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "swepfre.ngd" ...

Writing NGDBUILD log file "swepfre.bld"...

NGDBUILD done.




Started process "Map".

Using target part "4vsx55ff1148-11".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   21
Logic Utilization:
  Number of Slice Flip Flops:          16 out of  49,152    1%
  Number of 4 input LUTs:               7 out of  49,152    1%
Logic Distribution:
  Number of occupied Slices:                           10 out of  24,576    1%
    Number of Slices containing only related logic:      10 out of      10  100%
    Number of Slices containing unrelated logic:          0 out of      10    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:           7 out of  49,152    1%
  Number of bonded IOBs:                7 out of     640    1%
  Number of BUFG/BUFGCTRLs:             2 out of      32    6%
    Number used as BUFGs:                2
    Number used as BUFGCTRLs:            0
  Number of FIFO16/RAMB16s:             1 out of     320    1%
    Number used as FIFO16s:              0
    Number used as RAMB16s:              1
  Number of DSP48s:                     1 out of     512    1%
  Number of DCM_ADVs:                   1 out of       8   12%

Total equivalent gate count for design:  170
Additional JTAG gate count for IOBs:  336
Peak Memory Usage:  232 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "swepfre_map.mrp" for details.




Started process "Place & Route".




Constraints file: swepfre.pcf.
Loading device for application Rf_Device from file '4vsx55.nph' in environment
C:/Xilinx.
   "swepfre" is an NCD, version 3.1, device xc4vsx55, package ff1148, speed -11
This design is using the default stepping level (major silicon revision) for
this device (0). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '1'. Additional information on "stepping
level" is available at support.xilinx.com.

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)


Device speed data version:  "ADVANCED 1.52 2005-01-22".


Device Utilization Summary:

   Number of BUFGs                     2 out of 32      6%
   Number of DCM_ADVs                  8 out of 8     100%
   Number of DSP48s                    1 out of 512     1%
   Number of External IOBs             7 out of 640     1%
      Number of LOCed IOBs             0 out of 7       0%

   Number of PMVs                      1 out of 1     100%
   Number of RAMB16s                   1 out of 320     1%
   Number of Slices                   10 out of 24576   1%
      Number of SLICEMs                0 out of 12288   0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_1 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_1 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_2 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_2 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_3 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_3 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_4 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_4 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_5 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_5 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_6 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_6 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKFX_7 has no load
WARNING:Par:276 - The signal XIL_ML_UNUSED_DCM_CLKOUT_7 has no load

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98972d) REAL time: 8 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 8 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 10 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 10 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 11 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 11 secs 

Phase 7.8
.
Phase 7.8 (Checksum:9a758f) REAL time: 11 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 11 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 11 secs 

Phase 10.27
Phase 10.27 (Checksum:5f5e0f6) REAL time: 11 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 11 secs 

Writing design to file swepfre.ncd


Total REAL time to Placer completion: 12 secs 
Total CPU time to Placer completion: 9 secs 

Starting Router

Phase 1: 275 unrouted;       REAL time: 19 secs 

Phase 2: 73 unrouted;       REAL time: 19 secs 

Phase 3: 10 unrouted;       REAL time: 19 secs 

Phase 4: 0 unrouted;       REAL time: 19 secs 

Total REAL time to Router completion: 19 secs 
Total CPU time to Router completion: 12 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|             XLXN_13 |BUFGCTRL_X0Y13| No   |    7 |  0.053     |  3.215      |
+---------------------+--------------+------+------+------------+-------------+
|              XLXN_4 |         Local|      |    5 |  0.306     |  1.255      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 24 secs 
Total CPU time to PAR completion: 15 secs 

Peak Memory Usage:  212 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 14
Number of info messages: 1

Writing design to file swepfre.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '4vsx55.nph' in environment
C:/Xilinx.
   "swepfre" is an NCD, version 3.1, device xc4vsx55, package ff1148, speed -11
This design is using the default stepping level (major silicon revision) for
this device (0). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '1'. Additional information on "stepping
level" is available at support.xilinx.com.

Analysis completed Fri Oct 05 09:54:08 2007
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 13 secs 


Project Navigator Auto-Make Log File
-------------------------------------



DRC Check completed: No Error found.
Vhdl testbench file generated.


Project Navigator Auto-Make Log File
-------------------------------------





Project Navigator Auto-Make Log File
-------------------------------------




Started process "Compile HDL Simulation Libraries".

XILINX = 'C:\Xilinx'
Library Source => 'C:\Xilinx'

Compilation Mode = FAST
Scheduling Smart-Model library installation & compilation for VIRTEX-4 

Installing Xilinx Smart-Model.....

	-> Environment variable LMC_HOME isn't set, or its path doesn't exist.
	-> Installtion directory isn't defined in compxlib.cfg
	-> Use default installation directory: C:\Xilinx\smartmodel\nt\installed_nt
	-> Set environment variable LMC_HOME = C:\Xilinx\smartmodel\nt\installed_nt
	-> Creating installation directory : 'C:\Xilinx\smartmodel\nt\installed_nt'
	-> Extracting model names from C:\Xilinx\smartmodel\nt\image\sl_toc.dat
	-> Creating 'model.list' at current directory

Library Image directory : 'C:\Xilinx\smartmodel\nt\image'
Installaltion directory : 'C:\Xilinx\smartmodel\nt\installed_nt'
Running installer...... 

Synopsys/Logic Modeling sl_admin
Copyright (c) 1984-2000 Synopsys Inc. ALL RIGHTS RESERVED
Version: 02042

Reading Media
Checking user selections
Loading models....
Loading model: dcc_fpgacore_swift, version: 02401, platform: pcnt
Loading model: emac_swift, version: 01020, platform: pcnt
Loading model: glogic_adv_swift, version: 01003, platform: pcnt
Loading model: glogic_swift, version: 04000, platform: pcnt
Loading model: gt10_swift, version: 02218, platform: pcnt
Loading model: gt11_swift, version: 01009, platform: pcnt
Loading model: gt_swift, version: 01601, platform: pcnt
Loading model: ppc405_adv_swift, version: 01007, platform: pcnt
Loading model: ppc405_swift, version: 04002, platform: pcnt
Updating Configuration files
Writing: C:\Xilinx\smartmodel\nt\installed_nt/data/pcnt.lmc
Updating Library Versioned links
Updating Documentation files
Updating Library cache
Install complete

'\vsim.exe' 不是内部或外部命令，也不是可运行的程序
或批处理文件。
Compiling Xilinx HDL Libraries for ModelSim SE Simulator
Language => vhdl
Backing up setup files if any...
Source Tools ('AUTO_DETECT') => [null]

ERROR:CAEInterfaces:326 - COMPXLIB[env]: unable to find simulator (mti_se) executables

<ToolTip>: Specify the simulator executable path in the "Simulator Path"
           property under "Compile HDL Simulation Libraries" properties.

           IMPORTANT: Make sure that the license file/other environment
           variable for mti_se are properly set

Log file (compxlib.log) generated.

ERROR: compxlib failed
Process "Compile HDL Simulation Libraries" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Compile HDL Simulation Libraries".

XILINX = 'C:\Xilinx'
Library Source => 'C:\Xilinx'

Compilation Mode = FAST
Scheduling Smart-Model library installation & compilation for VIRTEX-4 

Installing Xilinx Smart-Model.....

	-> Environment variable  LMC_HOME = c:\Xilinx\smartmodel\nt\installed_nt
	-> Extracting model names from C:\Xilinx\smartmodel\nt\image\sl_toc.dat
	-> Creating 'model.list' at current directory

Library Image directory : 'C:\Xilinx\smartmodel\nt\image'
Installaltion directory : 'c:\Xilinx\smartmodel\nt\installed_nt'
Running installer...... 

Synopsys/Logic Modeling sl_admin
Copyright (c) 1984-2000 Synopsys Inc. ALL RIGHTS RESERVED
Version: 02042

Reading Library
Reading Media
Checking user selections
Loading models....
Loading model: dcc_fpgacore_swift, version: 02401, platform: pcnt
Loading model: emac_swift, version: 01020, platform: pcnt
Loading model: glogic_adv_swift, version: 01003, platform: pcnt
Loading model: glogic_swift, version: 04000, platform: pcnt
Loading model: gt10_swift, version: 02218, platform: pcnt
Loading model: gt11_swift, version: 01009, platform: pcnt
Loading model: gt_swift, version: 01601, platform: pcnt
Loading model: ppc405_adv_swift, version: 01007, platform: pcnt
Loading model: ppc405_swift, version: 04002, platform: pcnt
Updating Configuration files
Writing: c:\Xilinx\smartmodel\nt\installed_nt/data/pcnt.lmc